DS90CP04_14 Datasheet, PDF (4/25 Pages) Texas Instruments – DS90CP04 1.5 Gbps 4x4 LVDS Crosspoint Switch

DS90CP04
SNLS154I – JANUARY 2002 – REVISED APRIL 2013
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Pin
Name
Pin
Number
I/O, Type
DIGITAL CONTROL INTERFACE
SCLK
6
I, LVCMOS
SI / SEL1
7
SEL0
5
CSO
18
RSO
2
I, LVCMOS
I, LVCMOS
O, LVCMOS
CSCLK
RSCLK
LOAD
19
O, LVCMOS
3
22
I, LVCMOS
MODE
23
I, LVCMOS
POWER
V_DD
GND
1, 8, 17,
24
4, 20, 21,
DAP
I, Power
I, Power
PIN DESCRIPTIONS (continued)
Description
Control clock to latch in programming data at SI. SCLK can be 0 MHz to 100 MHz. SCLK
should be burst of clock pulses active only while accessing the device. After completion of
programming, SCLK should be kept at logic low to minimize potential noise injection into
the high-speed differential data paths.
Programming data to select the switch configuration. Data is latched into the input buffer
register at the rising edge of SCLK.
Programming data to select the switch configuration.
With MODE low, control data is shifted out at CSO (RSO) for cascading to the next device
in the serial chain. The control data at CSO (RSO) is identical to that shifted in at SI with
the exception of the device column (row) address being decremented by one internally
before propagating to the next device in the chain. CSO (RSO) is clocked out at the rising
edge of SCLK.
With MODE low, these pins function as a buffered control clock from SCLK. CSCLK
(RSCLK) is used for cascading the serial control bus to the next device in the serial chain.
When LOAD is high and SCLK makes a LH transition, the device transfers the
programming data in the load register into the configuration registers. The new switch
configuration for all outputs takes effect. LOAD needs to remain high for only one SCLK
cycle to complete the process, holding LOAD high longer repeats the transfer to the
configuration register.
When MODE is low, the SCLK is active and a buffered SCLK signal is present at the
CLKOUT output. When MODE is high, the SCLK signal is uncoupled from register and
state machine internals. Internal registers will see an active low signal until MODE is
brought Low again.
V_DD = 2.5V ±5%. At least 4 low ESR 0.01 µF bypass capacitors should be connected from
V_DD to GND plane.
Ground reference to LVDS and CMOS circuitry.
DAP is the exposed metal contact at the bottom of the WQFN-32 package. The DAP is
used as the primary GND connection to the device. It should be connected to the ground
plane with at least 4 vias for optimal AC and thermal performance.
Serial Interface Truth Table
LOAD
0
0
MODE
0
1
SCLK
LH
LH
LH
0
X
1
1
LH
Resulting Action
The current state on SI is clocked into the input shift register.
Uncouples SCLK input from internal registers and state machine inputs. The RSCLK and
CSCLK outputs will drive an active Low signal until MODE is brought Low again. See
Configuration Select Truth Table below.
Loads OUT1–OUT4 configuration information from last valid frame. Places contents of load
register into the configuration register. The switch configuration is updated asynchronously
from the SCLK input.
Uncouples SCLK input from internal registers and state machine inputs. The RSCLK and
CSCLK outputs will drive an active Low signal until MODE is brought Low again. See
Configuration Select Truth Table below.
Configuration Select Truth Table
MODE
0
1
1
1
1
SEL1
X
0
0
1
1
SEL0
X
0
1
0
1
Resulting Action
The SEL0/1 pins only function in configuration select mode. See below.
Distribution: IN1 - OUT1 OUT2 OUT3 OUT4
Distribution: IN2 - OUT1 OUT2 OUT3 OUT4
Redundancy: IN1 - OUT1 OUT2 and IN3 - OUT3 OUT4
Broadside: IN1 - OUT1, IN2 - OUT2, IN3 - OUT3, IN4 - OUT4
4
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