TMS320TCI6604 Datasheet, PDF (77/223 Pages) Texas Instruments – Multicore Fixed and Floating-Point Digital Signal Processor

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TMS320TCI6604
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS783C—February 2012
Table 3-9
Reset Status Clear Register (RESET_STAT_CLR) Field Descriptions
Bit Field
31 GR
30-4 Reserved
3
LR3
2
LR2
1
LR1
0
LR0
End of Table 3-9
Description
Global Reset Clear bit
0 = Writing a 0 has no effect.
1 = Writing a 1 to the GR bit clears the corresponding bit in the RESET_STAT register.
Reserved
CorePac3 reset clear bit
0 = Writing a 0 has no effect.
1 = Writing a 1 to the LR3 bit clears the corresponding bit in the RESET_STAT register.
CorePac2 reset clear bit
0 = Writing a 0 has no effect.
1 = Writing a 1 to the LR2 bit clears the corresponding bit in the RESET_STAT register.
CorePac1 reset clear bit
0 = Writing a 0 has no effect.
1 = Writing a 1 to the LR1 bit clears the corresponding bit in the RESET_STAT register.
CorePac0 reset clear bit
0 = Writing a 0 has no effect.
1 = Writing a 1 to the LR0 bit clears the corresponding bit in the RESET_STAT register.
3.3.9 Boot Complete (BOOTCOMPLETE) Register
The BOOTCOMPLETE register controls the BOOTCOMPLETE pin status. The purpose is to indicate the
completion of the ROM booting process. The Boot Complete Register is shown in Figure 3-8 and described in
Table 3-10.
Figure 3-8 Boot Complete Register (BOOTCOMPLETE)
31
4
3
2
1
0
Reserved
BC3
BC2
BC1
BC0
R, + 0000 0000 0000 0000 0000 0000
RW,+0 RW,+0 RW,+0 RW,+0
Legend: R = Read only; RW = Read/Write; -n = value after reset
Table 3-10 Boot Complete Register (BOOTCOMPLETE) Field Descriptions
Bit Field
31-4 Reserved
3
BC3
2
BC2
1
BC1
0
BC0
End of Table 3-10
Description
Reserved
CorePac3 boot status
0 = CorePac3 boot NOT complete
1 = CorePac3 boot complete
CorePac2 boot status
0 = CorePac2 boot NOT complete
1 = CorePac2 boot complete
CorePac1 boot status
0 = CorePac1 boot NOT complete
1 = CorePac1 boot complete
CorePac0 boot status
0 = CorePac0 boot NOT complete
1 = CorePac0 boot complete
Copyright 2012 Texas Instruments Incorporated
Device Configuration 77