TMS320TCI6604 Datasheet, PDF (34/223 Pages) Texas Instruments – Multicore Fixed and Floating-Point Digital Signal Processor

TMS320TCI6604
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS783C—February 2012
2.5.3 PLL Boot Configuration Settings
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The PLL default settings are determined by the BOOTMODE[12:10] bits. The table below shows settings for various
input clock frequencies.
Table 2-13
C66x DSP System PLL Configuration ⁽¹⁾
800 MHz Device 1000 MHz Device
1200 MHz Device
1250 MHz Device
PASS PLL = 350 MHz ⁽²⁾
BOOTMODE Input Clock
[12:10]
Freq (MHz)
0b000
50.00
0 31 800 0 39 1000 0 47 1200 0 31 800 0 41
0b001
66.67
0 23 800.04 0 29 1000.05 0 35 1200.06 0 23 800.04 1 62
0b010
80.00
0 19 800 0 24 1000 0 29 1200 0 19 800 3 104
0b011
100.00
0 15 800 0 19 1000 0 23 1200 0 15 800 0 20
0b100
156.25
24 255 800 4 63 1000 24 383 1200 24 255 800 24 335
0b101
250.00
4 31 800 0 7 1000 4 47 1200 4 31 800 4 41
0b110
312.50
24 127 800 4 31 1000 24 191 1200 24 127 800 24 167
0b111
122.88
End of Table 2-13
47 624 800 28 471 999.989 31 624 1200 47 624 800 11 204
1 The PLL boot configuration of initial silicon 1.0 may only support 800MHz, 1000MHz and 1200MHz frequencies by default.
2 The PASS PLL generates 1050 MHz and is internally divided by 3 to feed 350 MHz to the packet accelerator.
1050
1050.053
1050
1050
1050
1050
1050
1049.6
OUTPUT_DIVIDE is the value of the field of SECCTL[22:19]. This will set the PLL to the maximum clock setting
for the device (with OUTPUT_DIVIDE=2, by default).
CLK = CLKIN × (PLLM+1) ÷ (OUTPUT_DIVIDE × (PLLD+1))
The configuration for the PASS PLL is also shown. The PASS PLL is configured with these values only if the Ethernet
boot mode is selected with the input clock set to match the main PLL clock (not the PASS clock). See Table 2-3 for
details on configuring Ethernet boot mode. The output from the PASS PLL goes through an on-chip divider to
reduce the operating frequency before reaching the NETCP. The PASS PLL generates 1050 MHz, and after the chip
divider (=3), feeds 350 MHz to the NETCP.
The Main PLL is controlled using a PLL controller and a chip-level MMR. The DDR3 PLL and PASS PLL are
controlled by chip level MMRs. For details on how to set up the PLL see section 7.5 ‘‘Main PLL and PLL Controller’’
on page 129. For details on the operation of the PLL controller module, see the Phase Locked Loop (PLL) Controller
for KeyStone Devices User Guide in ‘‘Related Documentation from Texas Instruments’’ on page 66.
2.6 Second-Level Bootloaders
Any of the boot modes can be used to download a second-level bootloader. A second-level bootloader allows for any
level of customization to current boot methods as well as the definition of a completely customized boot.
34 Device Overview
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