TMS320TCI6604 Datasheet, PDF (30/223 Pages) Texas Instruments – Multicore Fixed and Floating-Point Digital Signal Processor

TMS320TCI6604
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS783C—February 2012
2.5.2.3 Ethernet (SGMII) Boot Device Configuration
Figure 2-5 Ethernet (SGMII) Device Configuration Fields
9
8
7
6
5
SerDes Clock Mult
Ext connection
4
Device ID
Table 2-6
Ethernet (SGMII) Configuration Field Descriptions
Bit
Field
Description
9-8 SerDes Clock Mult SGMII SerDes input clock. The output frequency of the PLL must be 1.25 GBs.
0 = ×8 for input clock of 156.25 MHz
1 = ×5 for input clock of 250 MHz
2 = ×4 for input clock of 312.5 MHz
3 = Reserved
7-6 Ext connection
External connection mode
0 = MAC to MAC connection, master with auto negotiation
1 = MAC to MAC connection, slave, and MAC to PHY
2 = MAC to MAC, forced link
3 = MAC to fiber connection
5
Device ID
End of Table 2-6
This value can range from 0 to 7 is used in the device ID field of the Ethernet-ready frame.
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3
Note—Both of the SGMII ports have been initialized for boot. The device can boot through either of the
ports. If only one SGMII port is used, then the other port will time out before the boot process completes.
2.5.2.4 PCI Boot Device Configuration
Extra device configuration is provided by the PCI bits in the DEVSTAT register.
Figure 2-6 PCI Device Configuration Fields
9
8
7
6
5
Reserved
BAR Config
Table 2-7
PCI Device Configuration Field Descriptions
Bit
Field
9
Reserved
8-5
BAR Config
4-3
Reserved
End of Table 2-7
Description
Reserved
PCIe BAR registers configuration
This value can range from 0 to 0xf. See Table 2-8.
Reserved
4
3
Reserved
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