TMS320TCI6604 Datasheet, PDF (118/223 Pages) Texas Instruments – Multicore Fixed and Floating-Point Digital Signal Processor

TMS320TCI6604
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS783C—February 2012
7.3 Power Sleep Controller (PSC)
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The Power Sleep Controller (PSC) controls overall device power by turning off unused power domains and gating
off clocks to individual peripherals and modules. The PSC provides the user with an interface to control several
important power and clock operations.
For information on the Power Sleep Controller, see the Power Sleep Controller (PSC) for KeyStone Devices User
Guide in ‘‘Related Documentation from Texas Instruments’’ on page 66.
7.3.1 Power Domains
The device has several power domains that can be turned on for operation or off to minimize power dissipation. The
global power/sleep controller (GPSC) is used to control the power gating of various power domains.
Table 7-6 shows the TMS320TCI6604 power domains.
Table 7-6
Power Domains
Domain Block(s)
0
Most peripheral logic
1
Per-core TETB and System TETB
2
Packet Coprocessor
3
PCIe
4
SRIO
5
HyperLink
6
Reserved
7
MSMC RAM
8
C66x CorePac 0, L1/L2 RAMs
9
C66x CorePac 1, L1/L2 RAMs
10
C66x CorePac 2, L1/L2 RAMs
11
C66x CorePac 3, L1/L2 RAMs
12
Reserved
13
Reserved
14
Reserved
15
Reserved
End of Table 7-6
Note
Cannot be disabled
RAMs can be powered down
Logic can be powered down
Logic can be powered down
Logic can be powered down
Logic can be powered down
Reserved
MSMC RAM can be powered down
L2 RAMs can sleep
L2 RAMs can sleep
L2 RAMs can sleep
L2 RAMs can sleep
Reserved
Reserved
Reserved
Reserved
Power Connection
Always on
Software control
Software control
Software control
Software control
Software control
Reserved
Software control
Software control via C66x core. For details, see the
C66x CorePac Reference Guide.
Reserved
Reserved
Reserved
Reserved
118 Peripheral Information and Electrical Specifications
Copyright 2012 Texas Instruments Incorporated