CC2500RGPR Datasheet, PDF (74/99 Pages) Texas Instruments – Low-Cost Low-Power 2.4 GHz RF Transceiver

CC2500
Bit Field Name
7:6 BS_PRE_KI[1:0]
5:4 BS_PRE_KP[1:0]
3 BS_POST_KI
2 BS_POST_KP
1:0 BS_LIMIT[1:0]
0x1A: BSCFG – Bit Synchronization Configuration
Reset R/W Description
1 (01)
2 (10)
1
1
0 (00)
R/W The clock recovery feedback loop integral gain to be used before a
sync word is detected (used to correct offsets in data rate):
Setting Clock recovery loop integral gain before sync word
0 (00) KI
1 (01) 2KI
2 (10) 3KI
3 (11) 4KI
R/W The clock recovery feedback loop proportional gain to be used
before a sync word is detected.
Setting Clock recovery loop proportional gain before sync word
0 (00) KP
1 (01) 2KP
2 (10) 3KP
3 (11) 4KP
R/W The clock recovery feedback loop integral gain to be used after a
sync word is detected.
Setting Clock recovery loop integral gain after sync word
0
Same as BS_PRE_KI
1
KI /2
R/W The clock recovery feedback loop proportional gain to be used after
a sync word is detected.
Setting Clock recovery loop proportional gain after sync word
0
Same as BS_PRE_KP
1
KP
R/W The saturation point for the data rate offset compensation algorithm:
Setting Data rate offset saturation (max data rate difference)
0 (00) ±0 (No data rate offset compensation performed)
1 (01) ±3.125% data rate offset
2 (10) ±6.25% data rate offset
3 (11) ±12.5% data rate offset
SWRS040C
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