CC2500RGPR Datasheet, PDF (43/99 Pages) Texas Instruments – Low-Cost Low-Power 2.4 GHz RF Transceiver

19.7 RX Termination Timer
CC2500 has optional functions for automatic
termination of RX after a programmable time.
The main use for this functionality is wake-on-
radio (WOR), but it may be useful for other
applications. The termination timer starts when
in RX state. The timeout is programmable with
the MCSM2.RX_TIME setting. When the timer
expires, the radio controller will check the
condition for staying in RX; if the condition is
not met, RX will terminate.
The programmable conditions are:
 MCSM2.RX_TIME_QUAL=0:
Continue
receive if sync word has been found
 MCSM2.RX_TIME_QUAL=1:
Continue
receive if sync word has been found or
preamble quality is above threshold (PQT)
If the system can expect the transmission to
have started when enabling the receiver, the
MCSM2.RX_TIME_RSSI function can be used.
The radio controller will then terminate RX if
the first valid carrier sense sample indicates
no carrier (RSSI below threshold). See Section
17.4 on page 35 for details on Carrier Sense.
CC2500
For OOK modulation, lack of carrier sense is
only considered valid after eight symbol
periods. Thus, the MCSM2.RX_TIME_RSSI
function can be used in OOK mode when the
distance between “1” symbols is 8 or less.
If RX terminates due to no carrier sense when
the MCSM2.RX_TIME_RSSI function is used,
or if no sync word was found when using the
MCSM2.RX_TIME timeout function, the chip
will always go back to IDLE if WOR is disabled
and back to SLEEP if WOR is enabled.
Otherwise, the MCSM1.RXOFF_MODE setting
determines the state to go to when RX ends.
This means that the chip will not automatically
go back to SLEEP once a sync word has been
received. It is therefore recommended to
always wake up the microcontroller on sync
word detection when using WOR mode. This
can be done by selecting output signal 6 (see
Table 33 on page 53) on one of the
programmable GDO output pins, and
programming the microcontroller to wake up
on an edge-triggered interrupt from this GDO
pin.
20 Data FIFO
The CC2500 contains two 64 byte FIFOs, one
for received data and one for data to be
transmitted. The SPI interface is used to read
from the RX FIFO and write to the TX FIFO.
Section 10.5 contains details on the SPI FIFO
access. The FIFO controller will detect
overflow in the RX FIFO and underflow in the
TX FIFO.
When writing to the TX FIFO it is the
responsibility of the MCU to avoid TX FIFO
overflow. A TX FIFO overflow will result in an
error in the TX FIFO content.
Likewise, when reading the RX FIFO the MCU
must avoid reading the RX FIFO past its
empty value, since an RX FIFO underflow will
result in an error in the data read out of the RX
FIFO.
The chip status byte that is available on the SO
pin while transferring the SPI header contains
the fill grade of the RX FIFO if the access is a
read operation and the fill grade of the TX
FIFO if the access is a write operation. Section
10.1 on page 22 contains more details on this.
The number of bytes in the RX FIFO and TX
FIFO can also be read from the status
registers RXBYTES.NUM_RXBYTES and
TXBYTES.NUM_TXBYTES respectively. If a
received data byte is written to the RX FIFO at
the exact same time as the last byte in the RX
FIFO is read over the SPI interface, the RX
FIFO pointer is not properly updated and the
last read byte is duplicated. To avoid this
problem one should never empty the RX FIFO
before the last byte of the packet is received.
For packet lengths less than 64 bytes it is
recommended to wait until the complete
packet has been received before reading it out
of the RX FIFO.
If the packet length is larger than 64 bytes the
MCU must determine how many bytes can be
read
from
the
RX
FIFO
(RXBYTES.NUM_RXBYTES-1) and the following
software routine can be used:
SWRS040C
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