CC2500RGPR Datasheet, PDF (26/99 Pages) Texas Instruments – Low-Cost Low-Power 2.4 GHz RF Transceiver

CC2500
The GDO0 pin can also be used for an on-chip
analog temperature sensor. By measuring the
voltage on the GDO0 pin with an external ADC,
the temperature can be calculated.
Specifications for the temperature sensor are
found in Section 4.7 on page 14.
With default PTEST register setting (0x7F) the
temperature sensor output is only available
when the frequency synthesizer is enabled
(e.g. the MANCAL, FSTXON, RX and TX
states). It is necessary to write 0xBF to the
PTEST register to use the analog temperature
sensor in the IDLE state. Before leaving the
IDLE state, the PTEST register should be
restored to its default value (0x7F).
11.3 Optional Radio Control Feature
The CC2500 has an optional way of controlling
the radio, by reusing SI, SCLK and CSn from
the SPI interface. This feature allows for a
simple three-pin control of the major states of
the radio: SLEEP, IDLE, RX and TX.
This optional functionality is enabled with the
MCSM0.PIN_CTRL_EN configuration bit.
State changes are commanded as follows:
When CSn is high the SI and SCLK is set to
the desired state according to Table 18. When
CSn goes low the state of SI and SCLK is
latched and a command strobe is generated
internally according to the control coding. It is
only possible to change state with this
functionality. That means that for instance RX
will not be restarted if SI and SCLK are set to
RX and CSn toggles. When CSn is low the SI
and SCLK has normal SPI functionality.
All pin control command strobes are executed
immediately, except the SPWD strobe, which is
delayed until CSn goes high.
CSn
1




0
SCLK
X
0
0
1
1
SPI
mode
SI
X
0
1
0
1
SPI
mode
Function
Chip unaffected by SCLK/SI
Generates SPWD strobe
Generates STX strobe
Generates SIDLE strobe
Generates SRX strobe
SPI mode (wakes up into
IDLE if in SLEEP/XOFF)
Table 18: Optional Pin Control Coding
12 Data Rate Programming
The data rate used when transmitting, or the
data rate expected in receive is programmed
by the MDMCFG3.DRATE_M and the
MDMCFG4.DRATE_E configuration registers.
The data rate is given by the formula below.
As the formula shows, the programmed data
rate depends on the crystal frequency.
  _{RDATA }
256  DRATE _ M
2²⁸
 2^{DRATE _ E} _{ f XOSC}
The following approach can be used to find
suitable values for a given data rate:
DRATE
_
E


^log _{2 }
 _
R_DATA  2²⁰
f _XOSC



DRATE _ M

R_DATA  2²⁸
f _XOSC  2 ^{DRATE _ E}
 256
If DRATE_M is rounded to the nearest integer
and becomes 256, increment DRATE_E and
use DRATE_M=0.
The data rate can be set from 1.2 kBaud to
500 kBaud with the minimum step size of:
Min Data
Rate
[kBaud]
0.8
3.17
6.35
12.7
25.4
50.8
101.6
203.1
406.3
Typical
Data Rate
[kBaud]
1.2/2.4
4.8
9.6
19.6
38.4
76.8
153.6
250
500
Max Data
Rate
[kBaud]
3.17
6.35
12.7
25.4
50.8
101.6
203.1
406.3
500
Data Rate
Step Size
[kBaud]
0.0062
0.0124
0.0248
0.0496
0.0992
0.1984
0.3967
0.7935
1.5869
Table 19: Data Rate Step Size
SWRS040C
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