TMS320C6671 Datasheet, PDF (71/241 Pages) Texas Instruments – Fixed and Floating-Point Digital Signal Processor

TMS320C6671
Fixed and Floating-Point Digital Signal Processor
www.ti.com
SPRS756—April 2011
3.3.17 Timer Output Selection Register (TOUTPSEL)
The timer output selection is handled within the control register TOUTSEL. The Timer Output Selection Register
is shown in Figure 3-15 and described in Table 3-17.
Figure 3-15 Timer Output Selection Register (TOUTPSEL)
31
10
9
5
4
0
Reserved
TOUTPSEL1
TOUTPSEL0
R,+000000000000000000000000
RW,+00001
RW,+00000
Legend: R = Read only; RW = Read/Write; -n = value after reset
Table 3-17 Timer Output Selection Field Description (TOUTPSEL)
Bit
31-10
9-5
Field
Reserved
TOUTPSEL1
4-0
TOUTPSEL0
End of Table 3-17
Description
Reserved
Output select for TIMO1
00000: TOUTL0
00001: TOUTH0
Output select for TIMO0
00000: TOUTL0
00001: TOUTH0
00010: TOUTL1
00011: TOUTH1
00100 to 11111: Reserved
00010: TOUTL1
00011: TOUTH1
00100 to 11111: Reserved
3.3.18 Reset Mux (RSTMUXx) Register
The software controls the Reset Mux block through the reset multiplex register (RSTMUX0). This register is located
in Bootcfg memory space. The Timer Output Selection Register is shown in Figure 3-16 and described in Table 3-18.
Figure 3-16 Reset Mux Register RSTMUXx
31
10
9
8
7
5
4
3
1
0
Reserved
EVTSTATCLR
Reserved
DELAY
EVTSTAT
OMODE
LOCK
R, +0000 0000 0000 0000 0000 00
RC, +0
R, +0
RW, +100
R, +0
RW, +000
RW, +0
Legend: R = Read only; RW = Read/Write; -n = value after reset; RC = Read only and write 1 to clear
Table 3-18 Reset Mux Register Field Descriptions (Part 1 of 2)
Bit Field
31-10 Reserved
9 EVTSTATCLR
8 Reserved
7-5 DELAY
Description
Reserved
0 = Writing O had no effect
1 = Writing 1 to this bit clears the EVTSTAT bit
Reserved
000b = 256 DSP/6 cycles delay between NMI & Local reset, when OMODE = 100b
001b = 512 DSP/6 cycles delay between NMI & Local reset, when OMODE=100b
010b = 1024 DSP/6 cycles delay between NMI & Local reset, when OMODE=100b
011b = 2048 DSP/6 cycles delay between NMI & Local reset, when OMODE=100b
100b = 4096 DSP/6 cycles delay between NMI & Local reset, when OMODE=100b (Default)
101b = 8192 DSP/6 cycles delay between NMI & Local reset, when OMODE=100b
110b = 16384 DSP/6 cycles delay between NMI & Local reset, when OMODE=100b
111b = 32768 DSP/6 cycles delay between NMI & Local reset, when OMODE=100b
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