TMS320C6671 Datasheet, PDF (220/241 Pages) Texas Instruments – Fixed and Floating-Point Digital Signal Processor

TMS320C6671
Fixed and Floating-Point Digital Signal Processor
SPRS756—April 2011
Figure 7-38 I²C Receive Timings
11
SDA
8
SCL
4
10
1
3
6
5
12
7
3
2
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9
14
13
Stop
Start
Repeated
Start
Table 7-80 I²C Switching Characteristics ⁽¹⁾
(see Figure 7-39)
No.
16 t_c(SCL)
17 t_{su(SCLH-SDAL)}
18 t_h(SDAL-SCLL)
19 t_w(SCLL)
20 t_w(SCLH)
21 t_d(SDAV-SDLH)
22 t_v(SDLL-SDAV)
23 t_w(SDAH)
24 t_r(SDA)
25 t_r(SCL)
26 t_f(SDA)
27 t_f(SCL)
28 t_d(SCLH-SDAH)
29 C_p
End of Table 7-80
Parameter
Cycle time, SCL
Setup time, SCL high to SDA low (for a repeated START
condition)
Hold time, SDA low after SCL low (for a START and a repeated
START condition)
Pulse duration, SCL low
Pulse duration, SCL high
Delay time, SDA valid to SCL high
Valid time, SDA valid after SCL low (For I²C bus devices)
Pulse duration, SDA high between STOP and START conditions
Rise time, SDA
Rise time, SCL
Fall time, SDA
Fall time, SCL
Delay time, SCL high to SDA high (for STOP condition)
Capacitance for each I²C pin
Standard Mode
Min
Max
10
4.7
4
4.7
4
250
0
4.7
1000
1000
300
300
4
10
1 C_b = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
Stop
Fast Mode
Min
2.5
0.6
Max Unit
ms
ms
0.6
1.3
0.6
100
0
1.3
20 + 0.1C_b ⁽¹⁾
20 + 0.1C_b ⁽¹⁾
20 + 0.1C_b ⁽¹⁾
20 + 0.1C_b ⁽¹⁾
0.6
ms
ms
ms
ns
0.9 ms
ms
300 ns
300 ns
300 ns
300 ns
ms
10 pF
220
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