TMS320C6671 Datasheet, PDF (33/241 Pages) Texas Instruments – Fixed and Floating-Point Digital Signal Processor

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TMS320C6671
Fixed and Floating-Point Digital Signal Processor
SPRS756—April 2011
Table 2-15 Terminal Functions — Signals and Control by Function (Part 1 of 12)
Signal Name
LENDIAN †
BOOTMODE00 †
BOOTMODE01†
BOOTMODE02 †
BOOTMODE03 †
BOOTMODE04 †
BOOTMODE05 †
BOOTMODE06 †
BOOTMODE07 †
BOOTMODE08 †
BOOTMODE09 †
BOOTMODE10 †
BOOTMODE11 †
BOOTMODE12 †
PCIESSMODE0 †
PCIESSMODE1 †
PCIESSEN †
CORECLKP
CORECLKN
SRIOSGMIICLKP
SRIOSGMIICLKN
DDRCLKP
DDRCLKN
PCIECLKP
PCIECLKN
MCMCLKP
MCMCLKN
PASSCLKP
PASSCLKN
AVDDA1
AVDDA2
AVDDA3
SYSCLKOUT
PACLKSEL
HOUT
NMI
LRESET
LRESETNMIEN
Ball No. Type
H25 IOZ
J28
IOZ
J29
IOZ
J26
IOZ
J25
IOZ
J27
IOZ
J24
IOZ
K27
IOZ
K28
IOZ
K26
IOZ
K29
IOZ
L28
IOZ
L29
IOZ
K25
IOZ
K24
IOZ
L27
IOZ
L24
I
AG3 I
AG4 I
AG6 I
AJ6
I
G29 I
H29 I
AG5 I
AH5 I
W2
I
Y2
I
AJ5
I
AJ4
I
H22 P
AC6 P
AD5 P
AE3
OZ
AE4
I
AD20 OZ
M25 I
N26 I
M27 I
IPD/IPU
UP
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
UP
UP
UP
UP
Description
Boot Configuration Pins
Endian configuration pin (Pin shared with GPIO[0])
See Section 2.5 ‘‘Boot Modes Supported and PLL Settings’’ on page 26 for more details
(Pins shared with GPIO[1:13])
PCIe Mode selection pins (Pins shared with GPIO[14:15])
PCIe module enable (Pin shared with TIMI0)
Clock / Reset
Core Clock Input to main PLL.
RapidIO/SGMII Reference Clock to drive the RapidIO and SGMII SerDes
DDR Reference Clock Input to DDR PLL (
PCIe Clock Input to drive PCIe SerDes
HyperLink Reference Clock to drive the HyperLink SerDes
Packet Sub-system Reference Clock
SYS_CLK PLL Power Supply Pin
DDR_CLK PLL Power Supply Pin
PS_SS_CLK PLL Power Supply Pin
System Clock Output to be used as a general purpose output clock for debug purposes
PA clock select to choose between core clock and PASSCLK pins
Interrupt output pulse created by IPCGRH
Non-maskable Interrupt
Warm Reset
Enable for core selects
Copyright 2011 Texas Instruments Incorporated
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