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TMS320C6671 Datasheet, PDF (217/241 Pages) Texas Instruments – Fixed and Floating-Point Digital Signal Processor
TMS320C6671
Fixed and Floating-Point Digital Signal Processor
www.ti.com
SPRS756—April 2011
7.11.2 DDR3 Memory Controller Electrical Data/Timing
The KeyStone DSP DDR3 Implementation Guidelines (literature number SPRABI1)specifies a complete DDR3
interface solution as well as a list of compatible DDR3 devices. The DDR3 electrical requirements are fully specified
in the DDR3 Jedec Specification JESD79-3C. TI has performed the simulation and system characterization to ensure
all DDR3 interface timings in this solution are met; therefore, no electrical data/timing information is supplied here
for this interface.
Note—TI supports only designs that follow the board design guidelines outlined in the application report.
7.12 I2C Peripheral
The inter-integrated circuit (I2C) module provides an interface between DSP and other devices compliant with
Philips Semiconductors Inter-IC bus (I2C bus) specification version 2.1 and connected by way of an I2C bus.
External components attached to this 2-wire serial bus can transmit/receive up to 8-bit data to/from the DSP
through the I2C module.
7.12.1 I2C Device-Specific Information
The TMS320C6671 device includes an I2C peripheral module. NOTE: when using the I2C module, ensure there are
external pullup resistors on the SDA and SCL pins.
The I2C modules on the C6671 may be used by the DSP to control local peripheral ICs (DACs, ADCs, etc.) or may
be used to communicate with other controllers in a system or to implement a user interface.
The I2C port supports:
• Compatible with Philips I2C specification revision 2.1 (January 2000)
• Fast mode up to 400 Kbps (no fail-safe I/O buffers)
• Noise filter to remove noise 50 ns or less
• 7-bit and 10-bit device addressing modes
• Multi-master (transmit/receive) and slave (transmit/receive) functionality
• Events: DMA, interrupt, or polling
• Slew-rate limited open-drain output buffers
Copyright 2011 Texas Instruments Incorporated
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