TMS320C6671 Datasheet, PDF (30/241 Pages) Texas Instruments – Fixed and Floating-Point Digital Signal Processor

TMS320C6671
Fixed and Floating-Point Digital Signal Processor
SPRS756—April 2011
2.5.2.5.2 I²C Passive Mode
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In passive mode, the device does not drive the clock, but simply acks data received on the specified address.
Figure 2-8
I²C Passive Mode Device Configuration Bit Fields
9
8
7
6
5
4
3
Mode
Receive I²C Address
Reserved
Table 2-10 I²C Passive Mode Device Configuration Field Descriptions
Bit Field
9
Mode
8-5 Receive I²C Address
4-3 Reserved
Value
0
1
0-15
0-3
Description
Master Mode (See ‘‘I2C Master Mode’’ on page 29)
Passive Mode
The I²C Bus address the device will listen to for data
Reserved
2.5.2.6 SPI Boot Device Configuration
In SPI boot mode, the SPI device configuration uses ten bits of device configuration instead of seven as used in other
boot modes.
Figure 2-9 SPI Device Configuration Bit Fields
12
11
10
9
Mode
4, 5 Pin
Addr Width
8
7
Chip Select
6
5
Parameter Table Index
4
3
Reserved
Table 2-11 SPI Device Configuration Field Descriptions
Bit
12-11
Field
Mode
10
4, 5 Pin
9
Addr Width
8-7
Chip Select
6-5
Parameter Table Index
4-3
Reserved
Value
Description
Clk Pol / Phase
0 Data is output on the rising edge of SPICLK. Input data is latched on the falling edge.
1 Data is output one half-cycle before the first rising edge of SPICLK and on subsequent falling edges.
Input data is latched on the rising edge of SPICLK.
2 Data is output on the falling edge of SPICLK. Input data is latched on the rising edge.
3 Data is output one half-cycle before the first falling edge of SPICLK and on subsequent rising edges.
Input data is latched on the falling edge of SPICLK.
0 4-pin mode used
1 5-pin mode used
0 16-bit address values are used
1 24-bit address values are used
0-3 The chip select field value
0-3 Specifies which parameter table is loaded
0-3 Reserved
30
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