THS1206-EP Datasheet, PDF (7/43 Pages) Texas Instruments – 12-BIT 6 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS

THS1206ĆEP
12ĆBIT 6 MSPS, SIMULTANEOUS SAMPLING
ANALOGĆTOĆDIGITAL CONVERTERS
SGLS126A − JULY 2002 − REVISED FEBRUARY 2003
timing specification of the single conversion mode^†
PARAMETER
tc
Clock cycle of the internal clock oscillator
t1
Pulse width, CONVST
tdA
Aperture time
t2
Time between consecutive start of single conversion
Delay time, DATA_AV becomes active for the trigger
level condition: TRIG0 = 0, TRIG1 = 0
Delay time, DATA_AV becomes active for the trigger
td(DATA_AV) _{level condition: TRIG0 = 1, TRIG1 = 0}
Delay time, DATA_AV becomes active for the trigger
level condition: TRIG0 = 0, TRIG1 = 1
Delay time, DATA_AV becomes active for the trigger
td(DATA_AV) _{level condition: TRIG0 = 1, TRIG1 = 1}
† _{Timing parameters are ensured by design but are not tested.}
TEST CONDITIONS
1 analog input
2 analog inputs
3 analog inputs
4 analog inputs
1 analog input
2 analog inputs
3 analog inputs
4 analog inputs
1 analog input, TL = 1
2 analog inputs, TL = 2
3 analog inputs, TL = 3
4 analog inputs, TL = 4
1 analog input, TL = 4
2 analog inputs, TL = 4
3 analog inputs, TL = 6
4 analog inputs, TL = 8
1 analog input, TL = 8
2 analog inputs, TL = 8
3 analog inputs, TL = 9
4 analog inputs, TL = 12
1 analog input, TL = 14
2 analog inputs, TL = 12
3 analog inputs, TL = 12
MIN
159
1.5×tc
2.5×tc
3.5×tc
4.5×tc
2×tc
3×tc
4×tc
5×tc
TYP MAX
UNIT
167
175 ns
ns
1
ns
ns
ns
6×tc
ns
7×tc
8×tc
9×tc
ns
3×t2 +6×tc
ns
t2 +7×tc
t2 +8×tc
ns
t2 +9×tc
7×t2 +6×tc
ns
3×t2 +7×tc
2×t2 +8×tc
2×t2 +9×tc
ns
13×t2 +6×tc
ns
5×t2 +7×tc
3×t2 +8×tc ns
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