THS1206-EP Datasheet, PDF (18/43 Pages) Texas Instruments – 12-BIT 6 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS

THS1206ĆEP
12ĆBIT 6 MSPS, SIMULTANEOUS SAMPLING
ANALOGĆTOĆDIGITAL CONVERTERS
SGLS126A − JULY 2002 − REVISED FEBRUARY 2003
analog input channel selection
The analog input channels of the THS1206 can be selected via bits 3 to 7 of control register 0. One single
channel (single-ended or differential) is selected via bit 3 and bit 4 of control register 0. Bit 5 controls the
selection between single-ended and differential configuration. Bit 6 and bit 7 select the autoscan mode, if more
than one input channel is selected. Table 10 shows the possible selections.
BIT 7
SCAN
0
0
0
0
0
0
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
BIT 6
DIFF1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
1
1
1
1
1
1
BIT 5
DIFF0
0
0
0
0
1
1
0
0
0
1
1
0
1
1
0
1
1
0
0
0
1
1
1
1
Table 10. Analog Input Channel Configurations
BIT 4 BIT 3
CHSEL1 CHSEL0
DESCRIPTION OF THE SELECTED INPUTS
0
0
Analog input AINP (single ended)
0
1
Analog input AINM (single ended)
1
0
Analog input BINP (single ended)
1
1
Analog input BINM (single ended)
0
0
Differential channel (AINP−AINM)
0
1
Differential channel (BINP−BINM)
0
1
Autoscan two single ended channels: AINP, AINM, AINP, …
1
0
Autoscan three single ended channels: AINP, AINM, BINP, AINP, …
1
1
Autoscan four single ended channels: AINP, AINM, BINP, BINM, AINP, …
Autoscan one differential channel and one single ended channel AINP, (BINP−BINM),
0
1
AINP, (BINP−BINM), …
1
0
Autoscan one differential channel and two single ended channel AINP, AINM, (BINP−
BINM), AINP, …
0
1
Autoscan two differential channels (AINP−AINM), (BINP−BINM), (AINP−AINM), …
1
0
Reserved
1
1
Reserved
0
0
Reserved
0
0
Reserved
1
1
Reserved
0
0
Reserved
1
0
Reserved
1
1
Reserved
0
0
Reserved
0
1
Reserved
1
0
Reserved
1
1
Reserved
test mode
The test mode of the ADC is selected via bit 8 and bit 9 of control register 0. The different selections are shown
in Table 11.
Table 11. Test Mode
BIT 9 BIT 8
TEST1 TEST0
OUTPUT RESULT
0
0
Normal mode
0
1
VREFP
1
0
((VREFM)+(VREFP))/2
1
1
VREFM
Three different options can be selected. This feature allows support testing of hardware connections between
the ADC and the processor.
18
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265