THS1206-EP Datasheet, PDF (25/43 Pages) Texas Instruments – 12-BIT 6 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS

THS1206ĆEP
12ĆBIT 6 MSPS, SIMULTANEOUS SAMPLING
ANALOGĆTOĆDIGITAL CONVERTERS
SGLS126A − JULY 2002 − REVISED FEBRUARY 2003
timing and signal description of the THS1206 (continued)
read timing (using RD, RD-controlled)
Figure 15 shows the read-timing behavior when the WR(R/W) input is programmed as a write-input only. The
input RD acts as the read-input in this configuration. This timing is called RD-controlled because RD is the last
external signal of CS0, CS1, and RD which becomes valid.
CS0
CS1
WR ^{ÎÎÎÎÎÎÎÎ}
RD
D(0−11)
DATA_AV
tsu(CS)
10%
tw(RD)
ta
90%
td(CSDAV)
90%
ÏÏÏÏÏÏ ^th(CS)
10%
th
90%
Figure 15. Read Timing Diagram Using RD (RD-controlled)
read timing parameter (RD-controlled)
PARAMETER
tsu(CS)
ta
td(CSDAV)
th
th(CS)
tw(RD)
Setup time, RD low to last CS valid
Access time, last CS valid to data valid
Delay time, last CS valid to DATA_AV inactive
Hold time, first CS invalid to data invalid
Hold time, RD change to first CS invalid
Pulse duration, RD active
MIN TYP MAX UNIT
0
ns
0
10 ns
12
ns
0
5 ns
5
ns
10
ns
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