DS64EV100_15 Datasheet, PDF (7/16 Pages) Texas Instruments – Programmable Single Equalizer

DS64EV100
www.ti.com
SNLS232E – OCTOBER 2006 – REVISED FEBRUARY 2013
PCB LAYOUT CONSIDERATIONS FOR DIFFERENTIAL PAIRS
The CML inputs and outputs must have a controlled differential impedance of 100Ω. It is preferable to route CML
lines exclusively on one layer of the board, particularly for the input traces. The use of vias should be avoided if
possible. If vias must be used, they should be used sparingly and must be placed symmetrically for each side of
a given differential pair. Route the CML signals away from other signals and noise sources on the printed circuit
board. See AN-1187 for additional information on WSON packages.
POWER SUPPLY BYPASSING
Two approaches are recommended to ensure that the DS64EV100 is provided with an adequate power supply.
First, the supply (V_DD) and ground (GND) pins should be connected to power planes routed on adjacent layers of
the printed circuit board. The layer thickness of the dielectric should be minimized so that the V_DD and GND
planes create a low inductance supply with distributed capacitance. Second, careful attention to supply
bypassing through the proper use of bypass capacitors is required. A 0.01μF bypass capacitor should be
connected to each V_DD pin such that the capacitor is placed as close as possible to the DS64EV100. Smaller
body size capacitors can help facilitate proper component placement. Additionally, three capacitors with
capacitance in the range of 2.2 μF to 10 μF should be incorporated in the power supply bypassing design as
well. These capacitors can be either tantalum or an ultra-low ESR ceramic and should be placed as close as
possible to the DS64EV100.
DC COUPLING
The DS64EV100 supports both AC coupling with external ac coupling capacitor, and DC coupling to its upstream
driver, or downstream receiver. With DC coupling, users must ensure the input signal common mode is within the
range of the electrical specification V_ICMDC and the device output is terminated with 50 Ω to V_DD.
TYPICAL PERFORMANCE EYE DIAGRAMS AND CURVES
Figure 7. Equalized Signal
(40 in FR4, 2.5 Gbps, PRBS7, 0x07 Setting)
Figure 8. Equalized Signal
(40 in FR4, 5 Gbps, PRBS7, 0x07 Setting)
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