DS64EV100_15 Datasheet, PDF (6/16 Pages) Texas Instruments – Programmable Single Equalizer

DS64EV100
SNLS232E – OCTOBER 2006 – REVISED FEBRUARY 2013
TIMING DIAGRAMS (continued)
V_DD
10k
IN +
50
6k
V_DD
EQ
50
10k
IN -
6k
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Figure 5. Simplified Receiver Input Termination Circuit
DS64EV100 APPLICATIONS INFORMATION
The DS64EV100 is a programmable equalizer optimized for operation up to 10 Gbps for backplane and cable
applications. The equalizer channel consists of an equalizer stage, a limiting amplifier, a DC offset correction
block, and a CML driver as shown in Figure 5.
DC Offset Correction
IN+
Input
IN -
Termination
Equalizer
BST CNTL
Limiting
Amplifier
OUT +
OUT-
BST_0 : BST_2
3
3
Figure 6. Simplified Block Diagram
EQUALIZER BOOST CONTROL
The equalizer channel supports eight programmable levels of equalization boost, and is controlled by the Boost
Set pins (BST_[2:0]) in accordance with Table 2. The eight levels of boost settings enables the DS64EV100 to
address a wide range of media loss and data rates.
6 mil Microstrip FR4
Trace Length (in)
0
5
10
15
20
25
30
40
Table 2. EQ Boost Control Table
24 AWG Twin-AX Cable
Length (m)
0
2
3
4
5
6
7
10
Channel Loss at 3.2 GHz
(db)
0
5
7.5
10
12.5
15
17
22
Channel Loss at 5 GHz
(dB)
0
6
10
14
18
21
24
30
BST_N
[2, 1, 0]
000
001
010
011
1 0 0 (Default)
101
110
111
GENERAL RECOMMENDATIONS
The DS64EV100 is a high performance circuit capable of delivering excellent performance. Careful attention
must be paid to the details associated with high-speed design as well as providing a clean power supply. Refer
to the LVDS Owner’s Manual for more detailed information on high-speed design tips to address signal integrity
design issues.
6
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