DS64EV100_15 Datasheet, PDF (4/16 Pages) Texas Instruments – Programmable Single Equalizer

DS64EV100
SNLS232E – OCTOBER 2006 – REVISED FEBRUARY 2013
Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless other specified. ^{(1) (2)}
PARAMETER
TEST CONDITIONS
MIN
POWER
I_IN
Input Current
V_IN = V_DD
V_IN = GND
−15
Input Leakage Current V_IN = GND, with internal pull-down resistors
I_IN-P
with Internal Pull-
Down/Up Resistors
V_IN = GND, with internal pull-up resistors
–20
CML RECEIVER INPUTS (IN+, IN−)
V_TX
Source Transmit Launch
Signal Level (IN diff)
AC-Coupled or DC-Coupled Requirement, Differential
measurement at point A.
Figure 1
400
V_INTRE
Input Threshold Voltage
Differential measurement at point B .
Figure 1
V_DDTX
Supply Voltage of
Transmitter to EQ
DC-Coupled Requirement
1.6
V_ICMDC
Input Common-Mode
Voltage
DC-Coupled Requirement Differential measurement at
point A.
Figure 1 ⁽⁴⁾
V_DDTX-0.8
R_LI
Differential Input Return
Loss
100 MHz – 3.2 GHz, with fixture’s effect de-embedded
R_IN
Input Resistance
Differential Across IN+ and IN-. Figure 4
85
CML OUTPUTS (OUT+, OUT−)
V_OD
Output Differential
Voltage Level (OUT diff)
Differential measurement with OUT+ and OUT-
terminated by 50Ω to GND, AC-Coupled
Figure 2
550
V_OCM
Output Common-Mode
Voltage
Single-ended measurement DC-Coupled with 50Ω
terminations
(5)
V_DD-0.2
t_R, t_F
Transition Time
20% to 80% of differential output voltage, measured
within 1” from output pins.
Figure 2
20
(5)
R_O
Output Resistance
Single-ended to V_DD
42
R_LO
Differential Output
Return Loss
100 MHz – 1.6 GHz, with fixture’s effect de-
embedded. IN+ = static high.
t_PLHD
t_PHLD
Differential Low to High
Propagation Delay
Differential High to Low
Propagation Delay
Propagation delay measurement at 50% V_OD between
input to output, 100 Mbps
Figure 3 ⁽⁵⁾
EQUALIZATION
DJ1
Residual Deterministic
Jitter at 10 Gbps
30” of 6 mil microstrip FR4, EQ Setting 0x06, PRBS-7
(2⁷-1) pattern
(6) (7)
DJ2
Residual Deterministic
Jitter at 6.4 Gbps
40” of 6 mil microstrip FR4, EQ Setting 0x06, PRBS-7
(2⁷-1) pattern
(6) (7)
DJ3
Residual Deterministic
Jitter at 5 Gbps
40” of 6 mil microstrip FR4, EQ Setting 0x07, PRBS-7
(2⁷-1) pattern
(6) (7)
DJ4
Residual Deterministic
Jitter at 2.5 Gbps
40” of 6 mil microstrip FR4, EQ Setting 0x07, PRBS-7
(2⁷-1) pattern
(6) (7)
TYP ⁽¹⁾
+1.8
0
+95
120
10
100
620
50
10
240
240
0.20
0.17
0.12
0.10
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MAX UNIT
+15 µA
µA
µA
µA
1600 mV_P-P
mV_P-P
V_DD
V
V_DDT
X^-0.2
V
dB
115 Ω
725 mV_P-P
V_DD-
0.1
V
60 ps
58 Ω
dB
ps
ps
UI_P-P
0.26 UI_P-P
0.20 UI_P-P
0.16 UI_P-P
(4) Measured with clock-like {11111 00000} pattern.
(5) Measured with clock-like {11111 00000} pattern.
(6) Specification is guaranteed by characterization at optimal boost setting and is not tested in production.
(7) Deterministic jitter is measured at the differential outputs (point C of Figure 1), minus the deterministic jitter before the test channel (point
A of Figure 1). Random jitter is removed through the use of averaging or similar means.
4
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