DS64EV100_15 Datasheet, PDF (5/16 Pages) Texas Instruments – Programmable Single Equalizer

DS64EV100
www.ti.com
SNLS232E – OCTOBER 2006 – REVISED FEBRUARY 2013
Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless other specified. ^{(1) (2)}
PARAMETER
TEST CONDITIONS
MIN
POWER
RJ
Random Jitter
(5) (8)
TYP ⁽¹⁾
0.5
MAX UNIT
ps_rms
(8) Random jitter contributed by the equalizer is defined as sqrt (J_OUT2 – J_IN2). J_OUT is the random jitter at equalizer outputs in ps_rms, see
point C of Figure 1; J_IN is the random jitter at the input of the equalizer in ps_rms, see Figure 1.
TIMING DIAGRAMS
Signal Source
A
B
C
6 mils Trace Width,
FR4 Microstrip Test Channel
SMA
Connector
SMA
Connector
DS64EV100
INPUT
OUTPUT
Figure 2. Test Setup Diagram
80%
OUT diff = (OUT+) ± (OUT-)
0V
20%
80%
20%
t_R
t_F
Figure 3. CML Output Transition Times
IN diff
0V
t_PLHD
t_PHLD
OUT diff
0V
Figure 4. Propagation Delay Timing Diagram
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