DRV8412_11 Datasheet, PDF (7/31 Pages) Texas Instruments – Dual Full Bridge PWM Motor Driver

www.ti.com
DRV8412
DRV8432
SLES242D – DECEMBER 2009 – REVISED JULY 2011
ELECTRICAL CHARACTERISTICS
T_A = 25 °C, PVDD = 50 V, GVDD = VDD = 12 V, f_Sw = 400 kHz, unless otherwise noted. All performance is in accordance
with recommended operating conditions unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
Internal Voltage Regulator and Current Consumption
V_REG
I_VDD
Voltage regulator, only used as a reference node
VDD supply current
VDD = 12 V
Idle, reset mode
Operating, 50% duty cycle
2.95 3.3 3.65 V
9 12 mA
10.5
I_{GVDD_X}
Gate supply current per half-bridge
Reset mode
Operating, 50% duty cycle
1.7 2.5 mA
8
I_{PVDD_X}
Output Stage
Half-bridge X (A, B, C, or D) idle current
Reset mode
0.7
1 mA
R_DS(on)
MOSFET drain-to-source resistance, low side (LS)
MOSFET drain-to-source resistance, high side (HS)
T_J = 25°C, GVDD = 12 V, Includes metallization
bond wire and pin resistance
T_J = 25°C, GVDD = 12 V, Includes metallization
bond wire and pin resistance
110
mΩ
110
mΩ
V_F
t_R
t_F
t_{PD_ON}
t_{PD_OFF}
t_DT
I/O Protection
Diode forward voltage drop
Output rise time
Output fall time
Propagation delay when FET is on
Propagation delay when FET is off
Dead time between HS and LS FETs
T_J = 25°C - 125°C, I_O = 5 A
Resistive load, I_O = 5 A
Resistive load, I_O = 5 A
Resistive load, I_O = 5 A
Resistive load, I_O = 5 A
Resistive load, I_O = 5 A
1
V
14
nS
14
nS
38
nS
38
nS
5.5
nS
V_uvp,G
V_uvp,hyst ⁽¹⁾
OTW ⁽¹⁾
OTW_hyst ⁽¹⁾
OTSD ⁽¹⁾
Gate supply voltage GVDD_X undervoltage
protection threshold
Hysteresis for gate supply undervoltage event
Overtemperature warning
Hysteresis temperature to reset OTW event
Overtemperature shut down
8.5
V
0.8
V
115 125 135 °C
25
°C
150
°C
OTE-
OTW_differential ⁽¹⁾
OTSD_HYST ⁽¹⁾
OTE-OTW overtemperature detect temperature
difference
Hysteresis temperature for FAULT to be released
following an OTSD event
25
°C
25
°C
I_OC
Overcurrent limit protection
I_OCT
Overcurrent response time
Resistor—programmable, nominal, R_OCP = 27 kΩ
Time from application of short condition to Hi-Z of
affected FET(s)
9.7
A
250
ns
R_PD
Internal pulldown resistor at the output of each
half-bridge
Connected when RESET_AB or RESET_CD is
active to provide bootstrap capacitor charge
1
kΩ
Static Digital Specifications
V_IH
High-level input voltage
V_IH
High-level input voltage
V_IL
Low-level input voltage
PWM_A, PWM_B, PWM_C, PWM_D, M1, M2, M3
2
RESET_AB, RESET_CD
2
PWM_A, PWM_B, PWM_C, PWM_D, M1, M2, M3,
RESET_AB, RESET_CD
3.6 V
5.5 V
0.8 V
l_lkg
Input leakage current
OTW / FAULT
–100
100 μA
R_{INT_PU}
Internal pullup resistance, OTW to VREG, FAULT to
VREG
20 26 35 kΩ
V_OH
High-level output voltage
Internal pullup resistor only
External pullup of 4.7 kΩ to 5 V
2.95 3.3 3.65
V
4.5
5
V_OL
Low-level output voltage
I_O = 4 mA
0.2 0.4 V
(1) Specified by design
Copyright © 2009–2011, Texas Instruments Incorporated
7