DRV8412_11 Datasheet, PDF (18/31 Pages) Texas Instruments – Dual Full Bridge PWM Motor Driver

DRV8412
DRV8432
SLES242D – DECEMBER 2009 – REVISED JULY 2011
APPLICATION INFORMATION
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SYSTEM DESIGN RECOMMENDATIONS
Voltage of Decoupling Capacitor
The voltage of the decoupling capacitors should be selected in accordance with good design practices.
Temperature, ripple current, and voltage overshoot must be considered. The high frequency decoupling capacitor
should use ceramic capacitor with X5R or better rating. For a 50-V application, a minimum voltage rating of 63 V
is recommended.
VREG Pin
The VREG pin is used for internal logic and not recommended to be used as a voltage source for external
circuitry.
VDD Pin
The transient current in VDD pin could be significantly higher than average current through that pin. A low
resistive path to GVDD should be used. A 22-µF to 47-µF capacitor should be placed on VDD pin beside the
100-nF to 1-µF decoupling capacitor to provide a constant voltage during transient.
OTW Pin
OTW reporting indicates the device approaching high junction temperature. This signal can be used with MCU to
decrease system power when OTW is low in order to prevent OT shut down at a higher temperature.
Mode Select Pin
Mode select pins (M1, M2, and M3) should be connected to either VREG (for logic high) or AGND for logic low. It
is not recommended to connect mode pins to board ground if 1-Ω resistor is used between AGND and GND.
Parallel Mode Operation
For a device operated in parallel mode, a minimum of 30 nH to 100 nH inductance or a ferrite bead is required
after the output pins (e.g. OUT_A and OUT_B) before connecting the two channels together. This will help to
prevent any shoot through between two paralleled channels during switching transient due to mismatch of
paralleled channels (e.g., processor variation, unsymmetrical PCB layout, etc).
TEC Driver Application
For TEC driver or other non-motor related applications (e.g. resistive load or dc output), a low-pass LC filter can
be used to meet the requirement.
PCB LAYOUT RECOMMENDATION
PCB Material Recommendation
FR-4 Glass Epoxy material with 2 oz. copper on both top and bottom layer is recommended for improved thermal
performance (better heat sinking) and less noise susceptibility (lower PCB trace inductance).
Ground Plane
Because of the power level of these devices, it is recommended to use a big unbroken single ground plane for
the whole system / board. The ground plane can be easily made at bottom PCB layer. In order to minimize the
impedance and inductance of ground traces, the traces from ground pins should keep as short and wide as
possible before connected to bottom ground plane through vias. Multiple vias are suggested to reduce the
impedance of vias. Try to clear the space around the device as much as possible especially at bottom PCB side
to improve the heat spreading.
Decoupling Capacitor
High frequency decoupling capacitors (100 nF) on PVDD_X pins should be placed close to these pins and with a
short ground return path to minimize the inductance on the PCB trace.
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