DRV8412_11 Datasheet, PDF (13/31 Pages) Texas Instruments – Dual Full Bridge PWM Motor Driver

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temperature-protection system that asserts an
active-low warning signal (OTW) when the device
junction temperature exceeds 125°C (nominal) and, if
the device junction temperature exceeds 150°C
(nominal), the device is put into thermal shutdown,
resulting in all half-bridge outputs being set in the
high-impedance (Hi-Z) state and FAULT being
asserted low. OTSD is latched in this case and
RESET_AB and RESET_CD must be asserted low to
clear the latch.
Undervoltage Protection (UVP) and Power-On
Reset (POR)
The UVP and POR circuits of the DRV8412/32 fully
protect the device in any power-up/down and
brownout situation. While powering up, the POR
circuit resets the overcurrent circuit and ensures that
all circuits are fully operational when the GVDD_X
and VDD supply voltages reach 9.8 V (typical).
Although GVDD_X and VDD are independently
monitored, a supply voltage drop below the UVP
threshold on any VDD or GVDD_X pin results in all
half-bridge outputs immediately being set in the
high-impedance (Hi-Z) state and FAULT being
asserted low. The device automatically resumes
operation when all supply voltage on the bootstrap
capacitors have increased above the UVP threshold.
DRV8412
DRV8432
SLES242D – DECEMBER 2009 – REVISED JULY 2011
DEVICE RESET
Two reset pins are provided for independent control
of half-bridges A/B and C/D. When RESET_AB is
asserted low, all four power-stage FETs in
half-bridges A and B are forced into a
high-impedance (Hi-Z) state. Likewise, asserting
RESET_CD low forces all four power-stage FETs in
half-bridges C and D into a high- impedance state. To
accommodate bootstrap charging prior to switching
start, asserting the reset inputs low enables weak
pulldown of the half-bridge outputs.
A rising-edge transition on reset input allows the
device to resume operation after a shut-down fault.
E.g., when either or both half-bridge A and B have
OC shutdown, a low to high transition of RESET_AB
pin will clear the fault and FAULT pin; when either or
both half-bridge C and D have OC shutdown, a low to
high transition of RESET_CD pin will clear the fault
and FAULT pin as well. When an OTSD occurs, both
RESET_AB and RESET_CD need to have a low to
high transition to clear the fault and FAULT signal.
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