CC1350 Datasheet, PDF (7/52 Pages) Texas Instruments – SimpleLink Ultra-Low-Power Dual-Band Wireless MCU

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CC1350
SWRS183 – JUNE 2016
4.2 Signal Descriptions – RGZ Package
PIN
NAME
NO.
DCDC_SW
33
DCOUPL
23
DIO_1
6
DIO_2
7
DIO_3
8
DIO_4
9
DIO_5
10
DIO_6
11
DIO_7
12
DIO_8
14
DIO_9
15
DIO_10
16
DIO_11
17
DIO_12
18
DIO_13
19
DIO_14
20
DIO_15
21
DIO_16
26
DIO_17
27
DIO_18
28
DIO_19
29
DIO_20
30
DIO_21
31
DIO_22
32
DIO_23
36
DIO_24
37
DIO_25
38
DIO_26
39
DIO_27
40
DIO_28
41
DIO_29
42
DIO_30
43
EGP
–
JTAG_TMSC
24
JTAG_TCKC
25
RESET_N
35
RF_N
2
RF_P
1
VDDR
45
Table 4-1. Signal Descriptions – RGZ Package
TYPE
DESCRIPTION
Power
Power
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital/Analog I/O
Digital/Analog I/O
Digital/Analog I/O
Digital/Analog I/O
Digital/Analog I/O
Digital/Analog I/O
Digital/Analog I/O
Digital/Analog I/O
Power
Digital I/O
Digital I/O
Digital input
RF I/O
RF I/O
Power
Output from internal DC-DC⁽¹⁾⁽²⁾
1.27-V regulated digital-supply (decoupling capacitor)⁽²⁾
GPIO, Sensor Controller
GPIO, Sensor Controller
GPIO, Sensor Controller
GPIO, Sensor Controller
GPIO, Sensor Controller, high-drive capability
GPIO, Sensor Controller, high-drive capability
GPIO, Sensor Controller, high-drive capability
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO, JTAG_TDO, high-drive capability
GPIO, JTAG_TDI, high-drive capability
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO, Sensor Controller, analog
GPIO, Sensor Controller, analog
GPIO, Sensor Controller, analog
GPIO, Sensor Controller, analog
GPIO, Sensor Controller, analog
GPIO, Sensor Controller, analog
GPIO, Sensor Controller, analog
GPIO, Sensor Controller, analog
Ground; exposed ground pad
JTAG TMSC, high-drive capability
JTAG TCKC⁽³⁾
Reset, active-low. No internal pullup.
Negative RF input signal to LNA during RX
Negative RF output signal from PA during TX
Positive RF input signal to LNA during RX
Positive RF output signal from PA during TX
1.7-V to 1.95-V supply, connect to output of internal DC-DC⁽⁴⁾⁽²⁾
(1) See technical reference manual listed in Section 8.3 for more details.
(2) Do not supply external circuitry from this pin.
(3) Important notice, for design consideration regrading noise immunity for this pin, refer to the JTAG Interface chapter in CC13xx, CC26xx
SimpleLink™ Wireless MCU Technical Reference Manual
(4) If internal DC-DC is not used, this pin is supplied internally from the main LDO.
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Terminal Configuration and Functions
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