CC1350 Datasheet, PDF (18/52 Pages) Texas Instruments – SimpleLink Ultra-Low-Power Dual-Band Wireless MCU

CC1350
SWRS183 – JUNE 2016
www.ti.com
5.12.4 Flash Memory Characteristics
T_c = 25°C, V_DDS = 3.0 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
Supported flash erase cycles before failure
Flash page or sector erase current
Flash page or sector erase time⁽¹⁾
Average delta current
Flash page or sector size
Flash write current
Flash write time⁽¹⁾
Average delta current, 4 bytes at a time
4 bytes at a time
(1) This number is dependent on flash aging and increases over time and erase cycles.
MIN TYP MAX UNIT
100
k Cycles
12.6
mA
8
ms
4
KB
8.15
mA
8
µs
5.12.5 ADC Characteristics
T_c = 25°C, V_DDS = 3.0 V, DC-DC disabled. Input voltage scaling enabled, unless otherwise noted⁽¹⁾
PARAMETER
TEST CONDITIONS
MIN
TYP
Input voltage range
0
Resolution
12
Sample rate
DNL ⁽³⁾
Offset
Gain error
Differential nonlinearity
Internal 4.3-V equivalent reference⁽²⁾
Internal 4.3-V equivalent reference⁽²⁾
2.1
–0.14
>–1
INL ⁽⁴⁾
Integral nonlinearity
±2
Internal 4.3-V equivalent reference⁽²⁾, 200 ksamples/s,
9.6-kHz input tone
10.0
ENOB Effective number of bits VDDS as reference, 200 ksamples/s, 9.6-kHz input tone
10.2
Internal 1.44-V reference, voltage scaling disabled,
32 samples average, 200 ksamples/s, 300-Hz input tone
11.1
Internal 4.3-V equivalent reference⁽²⁾, 200 ksamples/s,
9.6-kHz input tone
–65
THD
Total harmonic distortion VDDS as reference, 200 ksamples/s, 9.6-kHz input tone
–72
Internal 1.44-V reference, voltage scaling disabled,
32 samples average, 200 kspksamples/s, 300-Hz input tone
–75
SINAD
and
SNDR
Signal-to-noise and
distortion ratio
Internal 4.3-V equivalent reference⁽²⁾, 200 ksamples/s,
9.6-kHz input tone
VDDS as reference, 200 ksamples/s, 9.6-kHz input tone
Internal 1.44-V reference, voltage scaling disabled,
32 samples average, 200 ksamples/s, 300-Hz input tone
62
63
69
Internal 4.3-V equivalent reference⁽²⁾, 200 ksamples/s,
9.6-kHz input tone
74
SFDR
Spurious-free dynamic
range
VDDS as reference, 200 ksamples/s, 9.6-kHz input tone
75
Internal 1.44-V reference, voltage scaling disabled,
32 samples average, 200 ksamples/s, 300-Hz input tone
75
Conversion time
Including sampling time
5
Current consumption
Internal 4.3-V equivalent reference⁽²⁾
0.66
Current consumption
VDDS as reference
0.75
Reference voltage
Internal 4.3-V equivalent reference, voltage scaling enabled ⁽²⁾
4.3
Reference voltage
Internal 4.3-V equivalent reference, voltage scaling disabled ⁽²⁾
1.44
Reference voltage
VDDS as reference, voltage scaling disabled
VDDS /
2.82
Reference voltage
VDDS as reference, voltage scaling enabled
VDDS
Input Impedance
Capacitive input, Input impedance is depending on sampling time
and can be increased by increasing sampling time
>1
MAX
V_DDS
200
UNIT
V
Bits
ksamples/s
LSB
LSB
LSB
LSB
Bits
dB
dB
dB
µs
mA
mA
V
V
V
V
MΩ
(1) Using IEEE Std 1241™ 2010 for terminology and test methods.
(2) Input signal scaled down internally before conversion, as if voltage range was 0 to 4.3 V. Applied voltage must be within the absolute
maximum ratings (see Section 5.1) at all times.
(3) No missing codes. Positive DNL typically varies from 0.3 to 1.7, depending on the device (see Figure 5-7).
(4) For a typical example, see Figure 5-6.
18
Specifications
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