BUF16821-Q1 Datasheet, PDF (7/38 Pages) Texas Instruments – Programmable Gamma-Voltage Generator

www.ti.com
BUF16821-Q1
SBOS712 – MAY 2014
6.6 Timing Requirements
f_(SCL)
t_(BUF)
t_(HDSTA)
t_(SUSTA)
t_(SUSTO)
t_(HDDAT)
t_(SUDAT)
t_(LOW)
t_(HIGH)
t_R(SDA),
t_F(SDA)
t_R(SCL),
t_F(SCL)
t_R
PARAMETER
SCL operating frequency
Bus free time between stop and start conditions
Hold time after repeated start condition. After this period,
the first clock is generated.
Repeated start condition setup time
Stop condition setup time
Data hold time
Data setup time
SCL clock low period
SCL clock high period
Data rise and fall time
Clock rise and fall time
Clock and data rise time for SCLK ≤ 100 kHz
FAST MODE
MIN
MAX
0.001
0.4
1300
600
600
600
20
900
100
1300
600
300
HIGH-SPEED MODE
MIN
MAX
0.001
2.7
230
230
230
230
20
130
20
230
60
80
300
40
1000
UNIT
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t_(LOW)
t_R
t_F
t_(HDSTA)
SCL
SDA
t_(BUF)
P
S
t_(HDSTA)
t_(HIGH)
t_(HDDAT)
t_(SUSTA)
t_(SUDAT)
S
t_(SUSTO)
P
Figure 1. Timing Requirements Diagram
Copyright © 2014, Texas Instruments Incorporated
Product Folder Links: BUF16821-Q1
Submit Documentation Feedback
7