BUF16821-Q1 Datasheet, PDF (11/38 Pages) Texas Instruments – Programmable Gamma-Voltage Generator

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BUF16821-Q1
SBOS712 – MAY 2014
Feature Description (continued)
When all data are transferred, the master generates a stop condition, indicated by pulling SDA from low to high
while SCL is high. The device can act only as a slave device and therefore never drives SCL. SCL is an input
only for the BUF16821-Q1.
7.3.2 Data Rates
The two-wire bus operates in one of three speed modes:
• Standard: allows a clock frequency of up to 100 kHz;
• Fast: allows a clock frequency of up to 400 kHz; and
• High-speed mode (also called Hs mode): allows a clock frequency of up to 2.7 MHz.
The device is fully compatible with all three modes. No special action is required to use the device in standard or
fast modes, but high-speed mode must be activated. To activate high-speed mode, send a special address byte
of 00001 xxx, with SCL ≤ 400 kHz, following the start condition; where xxx are bits unique to the Hs-capable
master, which can be any value. This byte is called the Hs master code. Table 1 provides a reference for the
high-speed mode command code. (Note that this configuration is different from normal address bytes—the low
bit does not indicate read or write status.) The device responds to the high-speed command regardless of the
value of these last three bits. The device does not acknowledge this byte; the communication protocol prohibits
acknowledgment of the Hs master code. Upon receiving a master code, the device switches on its Hs mode
filters, and communicates at up to 2.7 MHz. Additional high-speed transfers may be initiated without resending
the Hs mode byte by generating a repeat start without a stop. The device switches out of Hs mode with the next
stop condition.
COMMAND
General-call reset
High-speed mode
Table 1. Quick-Reference of Command Codes
CODE
Address byte of 00h followed by a data byte of 06h.
00001xxx, with SCL ≤ 400 kHz; where xxx are bits unique to the Hs-capable master. This
byte is called the Hs master code.
7.3.3 General-Call Reset and Power-Up
The device responds to a general-call reset, which is an address byte of 00h (0000 0000) followed by a data byte
of 06h (0000 0110). The device acknowledges both bytes. Table 1 provides a reference for the general-call reset
command code. Upon receiving a general-call reset, the device performs a full internal reset, as though it was
powered off and then on. The device always acknowledges the general-call address byte of 00h (0000 0000), but
does not acknowledge any general-call data bytes other than 06h (0000 0110).
The device automatically performs a reset when powered up. As part of the reset, the device is configured for all
outputs to change to the last programmed nonvolatile memory values, or 1000000000 if the nonvolatile memory
values are not programmed.
7.3.4 Output Voltage
The buffer output values are determined by the analog supply voltage (V_S) and the decimal value of the binary
input code used to program that buffer. The value is calculated using Equation 1:
V_OUT = V_S ´
CODE₁₀
1024
(1)
The device outputs are capable of a full-scale voltage output change in typically 5 μs; no intermediate steps are
required.
7.3.5 Updating the DAC Output Voltages
Updating the digital-to-analog converter (DAC) and the VCOM register is not the same as updating the DAC and
VCOM output voltage because the device features a double-buffered register structure. There are two methods
for updating the DAC and VCOM output voltages.
Copyright © 2014, Texas Instruments Incorporated
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