BUF16821-Q1 Datasheet, PDF (13/38 Pages) Texas Instruments – Programmable Gamma-Voltage Generator

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BUF16821-Q1
SBOS712 – MAY 2014
To write to multiple DAC and VCOM registers:
1. Send a start condition on the bus.
2. Send the device address and read or write bit = low. The device acknowledges this byte.
3. Send either the OUT1 pointer address byte to start at the first DAC, or send the pointer address byte for
whichever DAC and VCOM is the first in the sequence of DACs and VCOMs to be updated. The device
begins with this DAC and VCOM and steps through subsequent DACs and VCOMs in sequential order.
4. Send the bytes of data; begin by sending the most significant byte (bits D15–D8, of which only bits D9 and
D8 have meaning, and bits D15–D14 must not be 01), followed by the least significant byte (bits D7–D0).
The first two bytes are for the DAC and VCOM addressed in the previous step. The DAC and VCOM register
is automatically updated after receiving the second byte. The next two bytes are for the following DAC and
VCOM. That DAC and VCOM register is updated after receiving the fourth byte. This process continues until
the registers of all following DACs and VCOMs are updated. The device continues to accept data for a total
of 18 DACs; however, the two data sets following the 16th data set are meaningless. The 19th and 20th data
sets apply to VCOM1 and VCOM2. The write disable bit cannot be accessed using this method. This bit must
be written to using the write to a single DAC register procedure.
5. Send a stop or start condition on the bus.
The device acknowledges each byte. To terminate communication, send a stop or start condition on the bus.
Only DAC registers that have received both bytes of data are updated.
7.3.7.3 Reading: DAC, VCOM, Other Register (Volatile Memory)
Reading a register returns the data stored in that DAC, VCOM, other register.
To read a single DAC, VCOM, other register:
1. Send a start condition on the bus.
2. Send the device address and read or write bit = low. The device acknowledges this byte.
3. Send the DAC, VCOM, other pointer address byte. Set bit D7 = 0 and D6 = 0; bits D5–D0 are the DAC,
VCOM, other address. Note that the device stores and returns data only from these addresses:
– 000000 through 001111
– 010010
– 010011
– 111100 through 111111
The device returns 0000 for reads from 010000 and 010001, and 010100 through 010111. See Table 4 for
valid DAC, VCOM, other addresses.
4. Send a start or stop and start condition.
5. Send the correct device address and read or write bit = high. The device acknowledges this byte.
6. Receive two bytes of data. These bytes are for the specified register. The most significant byte (bits D15–D8)
is received first; next is the least significant byte (bits D7–D0). In the case of DAC and VCOM channels, bits
D15–D10 have no meaning.
7. Acknowledge after receiving the first byte.
8. Send a stop or start condition on the bus or do not acknowledge the second byte to end the read transaction.
Communication may be terminated by sending a premature stop or start condition on the bus, or by not
acknowledging.
To read multiple registers:
1. Send a start condition on the bus.
2. Send the device address and read or write bit = low. The device acknowledges this byte.
3. Send either the OUT1 pointer address byte to start at the first DAC, or send the pointer address byte for
whichever register is the first in the sequence of DACs and VCOMs to be read. The device begins with this
DAC and VCOM and steps through subsequent DACs and VCOMs in sequential order.
4. Send a start or stop and start condition on the bus.
5. Send the correct device address and read or write bit = high. The device acknowledges this byte.
Copyright © 2014, Texas Instruments Incorporated
Product Folder Links: BUF16821-Q1
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