BUF16821-Q1 Datasheet, PDF (10/38 Pages) Texas Instruments – Programmable Gamma-Voltage Generator

BUF16821-Q1
SBOS712 – MAY 2014
7 Detailed Description
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7.1 Overview
The BUF16821-Q1 programmable voltage reference allows fast and easy adjustment of 16 programmable
gamma reference outputs and two VCOM outputs, each with 10-bit resolution. The device is programmed
through a high-speed, I²C interface. The final gamma and VCOM values can be stored in the onboard,
nonvolatile memory. To allow for programming errors or liquid crystal display (LCD) panel rework, the device
supports up to 16 write operations to the onboard memory. The device has two separate memory banks, allowing
simultaneous storage of two different gamma curves to facilitate dynamic switching between gamma curves.
Figure 19 illustrates a typical configuration of the device.
7.2 Functional Block Diagram
Digital
Analog
BKSEL ^{(2.0 V to 5.5 V) (9 V to 20 V)}
1
OUT1
OUT2
OUT15
OUT16
VCOM1
SDA
SCL
7.3 Feature Description
Control IF
A0
Device
VCOM2
7.3.1 Two-Wire Bus Overview
The device communicates over an industry-standard, two-wire interface to receive data in slave mode. This
standard uses a two-wire, open-drain interface that supports multiple devices on a single bus. Bus lines are
driven to a logic low level only. The device that initiates the communication is called a master, and the devices
controlled by the master are slaves. The master generates the serial clock on the clock signal line (SCL),
controls the bus access, and generates the start and stop conditions.
To address a specific device, the master initiates a start condition by pulling the data signal line (SDA) from a
high to a low logic level while SCL is high. All slaves on the bus shift in the slave address byte on the SCL rising
edge, with the last bit indicating whether a read or write operation is intended. During the ninth clock pulse, the
slave being addressed responds to the master by generating an acknowledge and pulling SDA low.
Data transfer is then initiated and eight bits of data are sent, followed by an acknowledge bit. During data
transfer, SDA must remain stable while SCL is high. Any change in SDA while SCL is high is interpreted as a
start or stop condition.
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