DM3730_11 Datasheet, PDF (68/280 Pages) Texas Instruments – Digital Media Processors

DM3730, DM3725
SPRS685D – AUGUST 2010 – REVISED JULY 2011
www.ti.com
BALL
PIN NAME [2]
NUMBER [1]
G22
E22
F22
J21
AC19
AB19
AD20
AC20
AD21
AC21
D24
E23
E24
F23
dss_pclk
gpio_66
hw_dbg12
safe_mode
dss_hsync
gpio_67
hw_dbg13
safe_mode
dss_vsync
gpio_68
safe_mode
dss_acbias
gpio_69
safe_mode
dss_data0
uart1_cts
gpio_70
safe_mode
dss_data1
uart1_rts
gpio_71
safe_mode
dss_data2
gpio_72
safe_mode
dss_data3
gpio_73
safe_mode
dss_data4
uart3_rx_ irrx
gpio_74
safe_mode
dss_data5
uart3_tx_ irtx
gpio_75
safe_mode
dss_data6
uart1_tx
gpio_76
hw_dbg14
safe_mode
dss_data7
uart1_rx
gpio_77
hw_dbg15
safe_mode
dss_data8
uart3_rx_irrx
gpio_78
hw_dbg16
safe_mode
dss_data9
uart3_tx_irtx
gpio_79
hw_dbg17
Table 2-3. Ball Characteristics (CUS Pkg.)⁽¹⁾ (continued)
MODE [3] TYPE [4]
0
O
4
IO
5
O
7
0
O
4
IO
5
O
7
0
O
4
IO
7
0
O
4
IO
7
0
IO
2
I
4
IO
7
0
IO
2
O
4
IO
7
0
IO
4
IO
7
0
IO
4
IO
7
0
IO
2
I
4
IO
7
0
IO
2
O
4
IO
7
0
IO
2
O
4
IO
5
O
7
0
IO
2
I
4
IO
5
O
7
0
IO
2
I
4
IO
5
O
7
0
IO
2
O
4
IO
5
O
BALL RESET BALL RESET RESET REL. POWER [8]
STATE [5] REL. STATE MODE [7]
[6]
H
H
7
vdds
HYS [9]
Yes
H
H
7
vdds
Yes
H
H
7
L
L
7
L
L
7
vdds
Yes
vdds
Yes
vdds
Yes
L
L
7
vdds
Yes
L
L
7
vdds
Yes
L
L
7
vdds
Yes
L
L
7
vdds
Yes
L
L
7
vdds
Yes
L
L
7
vdds
Yes
L
L
7
vdds
Yes
L
L
7
vdds
Yes
L
L
7
vdds
Yes
BUFFER
PULLUP
STRENGTH /DOWN
(mA) [10] TYPE [11]
8
PU/ PD
8
PU/ PD
8
PU/ PD
8
PU/ PD
8
PU/ PD
NA
8
8
8
PU/ PD
8
8
8
8
PU/ PD
8
8
8
PU/ PD
8
8
8
PU/ PD
NA
8
8
8
PU/ PD
8
8
8
8
PU/ PD
8
PU/ PD
8
PU/ PD
8
PU/ PD
IO CELL [12]
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
68
TERMINAL DESCRIPTION
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