DM3730_11 Datasheet, PDF (181/280 Pages) Texas Instruments – Digital Media Processors

DM3730, DM3725
www.ti.com
SPRS685D – AUGUST 2010 – REVISED JULY 2011
GPMC_FCLK
GNF12
gpmc_ncsx
GNF10
GNF15
gpmc_nbe0_cle
gpmc_nadv_ale
gpmc_noe
gpmc_a[16:1]
(gpmc_d[15:0])
GNF13
GNF14
DATA
gpmc_waitx
SWPS038-027
(1) GNF12 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional
clock cycles. From start of read cycle and after GNF12 functional clock cycles, input data will be internally sampled by active
functional clock edge. GNF12 value must be stored inside AccessTime register bits field.
(2) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.
(3) In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3.
Figure 6-15. GPMC / NAND Flash—Data Read Cycle
GPMC_FCLK
gpmc_ncsx
GNF1
GNF6
gpmc_nbe0_cle
gpmc_nadv_ale
gpmc_noe
gpmc_nwe
gpmc_a[16:1]
(gpmc_d[15:0])
GNF0
GNF9
GNF3
DATA
GNF4
(1) In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7.
Figure 6-16. GPMC / NAND Flash—Data Write Cycle
SWPS038-028
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Timing Requirements and Switching Characteristics 181
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