DM3730_11 Datasheet, PDF (2/280 Pages) Texas Instruments – Digital Media Processors

DM3730, DM3725
SPRS685D – AUGUST 2010 – REVISED JULY 2011
Bus
– Up to 8 Chip Select Pins With
128M-Byte Address Space per Chip
Select Pin
– Glueless Interface to NOR Flash,
NAND Flash (With ECC Hamming
Code Calculation), SRAM and
Pseudo-SRAM
– Flexible Asynchronous Protocol
Control for Interface to Custom Logic
(FPGA, CPLD, ASICs, etc.)
– Nonmultiplexed Address/Data Mode
(Limited 2K-Byte Address Space)
– 1.8-V I/O and 3.0-V (MMC1 only),
0.9-V to 1.2-V Adaptive Processor Core
Voltage
0.9-V to 1.1-V Adaptive Core Logic Voltage
Note: These are default Operating
Performance Point (OPP) voltages and could
be optimized to lower values using
SmartReflex AVS.
– Commercial, Industrial, and Extended
Temperature Grades
– Serial Communication
• 5 Multichannel Buffered Serial Ports
(McBSPs)
– 512 Byte Transmit/Receive Buffer
(McBSP1/3/4/5)
– 5K-Byte Transmit/Receive Buffer
(McBSP2)
– SIDETONE Core Support (McBSP2 and
3 Only) For Filter, Gain, and Mix
Operations
– Direct Interface to I2S and PCM Device
and T Buses
– 128 Channel Transmit/Receive Mode
• Four Master/Slave Multichannel Serial
Port Interface (McSPI) Ports
• High-Speed/Full-Speed/Low-Speed USB
OTG Subsystem (12-/8-Pin ULPI Interface)
• High-Speed/Full-Speed/Low-Speed
Multiport USB Host Subsystem
– 12-/8-Pin ULPI Interface or 6-/4-/3-Pin
Serial Interface
• One HDQ/1-Wire Interface
• Four UARTs (One with Infrared Data
Association [IrDA] and Consumer Infrared
[CIR] Modes)
• Three Master/Slave High-Speed
Inter-Integrated Circuit (I2C) Controllers
– Camera Image Signal Processing (ISP)
• CCD and CMOS Imager Interface
• Memory Data Input
• BT.601/BT.656 Digital YCbCr 4:2:2
(8-/10-Bit) Interface
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• Glueless Interface to Common Video
Decoders
• Resize Engine
– Resize Images From 1/4x to 4x
– Separate Horizontal/Vertical Control
– System Direct Memory Access (SDMA)
Controller (32 Logical Channels With
Configurable Priority)
– Comprehensive Power, Reset, and Clock
Management
• SmartReflex^TM Technology
• Dynamic Voltage and Frequency Scaling
(DVFS)
– ARM^® Cortex™-A8 Core
• ARMv7 Architecture
– TrustZone^®
– Thumb^®-2
– MMU Enhancements
• In-Order, Dual-Issue, Superscalar
Microprocessor Core
• NEON Multimedia Architecture
• Over 2x Performance of ARMv6 SIMD
• Supports Both Integer and Floating Point
SIMD
• Jazelle^® RCT Execution Environment
Architecture
• Dynamic Branch Prediction with Branch
Target Address Cache, Global History
Buffer, and 8-Entry Return Stack
• Embedded Trace Macrocell (ETM)
Support for Non-Invasive Debug
– ARM Cortex-A8 Memory Architecture:
• 32K-Byte Instruction Cache (4-Way
Set-Associative)
• 32K-Byte Data Cache (4-Way
Set-Associative)
• 256K-Byte L2 Cache
– 32K-Byte ROM
– 64K-Byte Shared SRAM
– Endianess:
• ARM Instructions - Little Endian
• ARM Data – Configurable
• DSP Instructions/Data - Little Endian
• Removable Media Interfaces:
– Three Multimedia Card (MMC)/ Secure Digital
(SD) With Secure Data I/O (SDIO)
• Test Interfaces
– IEEE-1149.1 (JTAG) Boundary-Scan
Compatible
– Embedded Trace Macro Interface (ETM)
– Serial Data Transport Interface (SDTI)
• 12 32-bit General Purpose Timers
• 2 32-bit Watchdog Timers
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DM3730, DM3725 Digital Media Processors
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