DM3730_11 Datasheet, PDF (191/280 Pages) Texas Instruments – Digital Media Processors

DM3730, DM3725
www.ti.com
SPRS685D – AUGUST 2010 – REVISED JULY 2011
6.5.1.2 Parallel Camera Interface (CPI)
6.5.1.2.1 CPI—Video and Graphics Digitizer 1.8V Mode
The imaging subsystem deals with the processing of the pixel data coming from an external image sensor
or from video and graphics digitizer. It is a key component for the following multimedia applications: video
preview, camera viewfinder, video record and still image capture. It supports RAW, RGB, and YUV data
processing.
Table 6-24 assumes testing over the recommended operating conditions and electrical characteristic
conditions below (see Figure 6-23 and Figure 6-24).
Table 6-23. CPI Timing Conditions—Video and Graphics Digitizer 1.8-V Mode
TIMING CONDITION PARAMETER
Input Conditions
t_R
Input signal rise time
t_F
Input signal fall time
VALUE
MIN
MAX
80
1800
80
1800
UNIT
ps
ps
Table 6-24. CPI Timing Requirements—Video and Graphics Digitizer 1.8-V Mode^{(4) (6)}
NO.
PARAMETER
OPP100
UNIT
ISP1
ISP2
ISP3
ISP4
1 / t_c(pclk)
t_w(pclkL)
t_w(pclkH)
t_dc(pclk)
t_J(pclk)
t_{su(vsV-pclkH)}
Frequency⁽¹⁾, input pixel clock cam_pclk
Typical pulse duration, input pixel clock cam_pclk low
Typical pulse duration, input pixel clock cam_pclk high
Duty cycle error, input pixel clock cam_pclk
Cycle jitter⁽³⁾, input pixel clock cam_pclk
Setup time, input vertical synchronization cam_vs valid before input
pixel clock cam_pclk rising/falling edge
MIN
MAX
148.5
0.5P⁽²⁾
0.5P⁽²⁾
0.5*P⁽²⁾ -
3.247
0.06P⁽²⁾
0.75
MHz
ns
ns
ns
ns
ns
ISP5
t_h(pclkH-vsV)
Hold time, input vertical synchronization cam_vs valid after input pixel
0.96
ns
clock cam_pclk rising/falling edge
ISP6
t_{su(hsV-pclkH)}
Setup time, input horizontal synchronization cam_hs valid before input
0.75
ns
pixel clock cam_pclk rising/falling edge
ISP7
t_h(pclkH-hsV)
Hold time, input horizontal synchronization cam_hs valid after input
0.96
ns
pixel clock cam_pclk rising/falling edge
ISP8
t_su(dV-pclkH)
Setup time, input data cam_d[n:0]⁽⁵⁾ valid before input pixel clock
0.75
ns
cam_pclk rising/falling edge
ISP9
t_h(pclkH-dV)
Hold time, input data cam_d[n:0]⁽⁵⁾ valid after input pixel clock
0.96
ns
cam_pclk rising/falling edge
ISP10 t_{su(wenV-pclkH)}
Setup time, input write enable cam_wen valid before input pixel clock
0.75
ns
cam_pclk rising/falling edge
ISP11 t_{h(pclkH-wenV)}
Hold time, input write enable cam_wen valid after input pixel clock
0.96
ns
cam_pclk rising/falling edge
ISP12 t_{su(fldV-pclkH)}
Setup time, input field identification cam_fld valid before input pixel
0.75
ns
clock cam_pclk rising/falling edge
ISP13 t_{h(pclkH-fldV)}
Hold time, input field identification cam_fld valid after input pixel clock
0.96
ns
cam_pclk rising/falling edge
(1) Related with the input maximum frequency supported by the ISP module in 8-bit mode with 8 to 16 data bits conversion bridge enabled.
(2) P = cam_pclk period in ns
(3) Maximum cycle jitter supported by cam_pclk input clock
(4) The timing requirements are assured up to the cycle jitter and duty cycle error conditions specified.
(5) n = 11 (Data bus size is limited to 8 bits. So the bits configuration is either cam_d[7:0] or cam_d[11:4]). Lines not connected must be
tied low.
(6) See Section 4.3.4, Processor Clocks.
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Timing Requirements and Switching Characteristics 191
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