TMS320DM8168 Datasheet, PDF (66/312 Pages) Texas Instruments – TMS320DM816x DaVinci Digital Media Processors

TMS320DM8168, TMS320DM8167
TMS320DM8166, TMS320DM8165
SPRS614 – MARCH 2011
www.ti.com
3.2.5 General-Purpose Memory Controller (GPMC) Signals
SIGNAL
NAME
GPMC_CLK/
GP1[29]
GPMC_CS[5] /
GPMC_A[12]
GPMC_CS[4] /
GP1[21]
GPMC_CS[3]
GPMC_CS[2]
GPMC_CS[1]
GPMC_CS[0]
GPMC_WE
GPMC_OE_RE
GPMC_BE1
GPMC_BE0_CLE
GPMC_ADV_ALE
GPMC_DIR/
GP1[20]
GPMC_WP
GPMC_WAIT
Table 3-6. GPMC Terminal Functions
NO.
V1
AG1
AG3
AG9
AH2
AH1
AH7
AG2
AF2
AF1
AE11
AE10
AE7
AE9
AE8
TYPE ⁽¹⁾ OTHER^{(2) (3)}
MUXED
DESCRIPTION
PULL: IPD / DIS
O
DRIVE: L / L
DVDD_3P3
GP1
GPMC Clock output
O
PULL: IPU / IPU
DRIVE: H / H
DVDD_3P3
GPMC
PINCTRL212
GPMC Chip Select 5
O
PULL: IPU / IPU
DRIVE: H / H
DVDD_3P3
GP1
PINCTRL211
GPMC Chip Select 4
O
PULL: IPU / IPU
DRIVE: H / H
DVDD_3P3
-
PINCTRL210
GPMC Chip Select 3
O
PULL: IPU / IPU
DRIVE: H / H
DVDD_3P3
-
PINCTRL209
GPMC Chip Select 2
O
PULL: IPU / IPU
DRIVE: H / H
DVDD_3P3
-
PINCTRL208
GPMC Chip Select 1
O
PULL: IPU / IPU
DRIVE: H / H
DVDD_3P3
-
PINCTRL207
GPMC Chip Select 0
O
PULL: IPU / IPU
DRIVE: H / H
DVDD_3P3
-
PINCTRL213
GPMC Write Enable output
O
PULL: IPU / DIS
DRIVE: H / H
DVDD_3P3
-
PINCTRL214
GPMC Output Enable output
O
PULL: IPU / DIS
DRIVE: H / H
DVDD_3P3
-
PINCTRL216
GPMC Upper Byte Enable output
O
PULL: IPU / DIS
DRIVE: H / L
DVDD_3P3
-
PINCTRL215
GPMC Lower Byte Enable output or Command Latch
Enable output
O
PULL: IPU / DIS
DRIVE: H / L
DVDD_3P3
-
PINCTRL217
GPMC Address Valid output or Address Latch Enable
output
O
PULL: IPD / DIS
DRIVE: L / H
DVDD_3P3
GP1
PINCTRL218
GPMC Direction Control for External Transceivers
O
PULL: IPU / IPD
DRIVE: H / L
DVDD_3P3
-
PINCTRL219
GPMC Write Protect output
I
PULL: IPD / IPD
DRIVE: Z / Z
DVDD_3P3
-
PINCTRL220
GPMC Wait input
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal.
(2) PULL: A / B, where:
A is the state of the internal pull resistor during POR reset
B is the state of the internal pull resistor after POR and Warm reset are de-asserted and during Warm reset
IPD = Internal Pulldown Enabled, IPU = Internal Pullup Enabled, DIS = Internal Pull Disabled
DRIVE: A / B, where;
A is the driving state of the pin during POR reset
B is the driving state of the pin after POR and Warm reset are de-asserted and during Warm reset
H = Driving High, L = Driving Low, Z = 3-State
For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see
Section 4.2.1, Pullup/Pulldown Resistors.
(3) Specifies the operating I/O supply voltage for each signal.
66
Device Pins
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