TMS320DM8168 Datasheet, PDF (30/312 Pages) Texas Instruments – TMS320DM816x DaVinci Digital Media Processors

TMS320DM8168, TMS320DM8167
TMS320DM8166, TMS320DM8165
SPRS614 – MARCH 2011
www.ti.com
Table 2-26. L4 Standard Peripheral Memory Map (continued)
DEVICE NAME
OCP Watchpoint
Reserved
Reserved
Reserved
Reserved
Reserved
DDR0 Phy Ctrl Regs
DDR1 Phy Ctrl Regs
Reserved
Interrupt controller⁽¹⁾
Reserved ⁽¹⁾
MPUSS config
register ⁽¹⁾
Reserved ⁽¹⁾
Reserved ⁽¹⁾
Reserved
START ADDRESS
(HEX)
0x4818 C000
0x4818 D000
0x4818 E000
0x4818 F000
0x4819 0000
0x4819 1000
0x4819 2000
0x4819 3000
0x4819 4000
0x4819 5000
0x4819 6000
0x4819 7000
0x4819 8000
0x4819 9000
0x4819 A000
0x4819 B000
0x4819 C000
0x4820 0000
0x4820 1000
0x4824 0000
END ADDRESS (HEX)
0x4818 CFFF
0x4818 DFFF
0x4818 EFFF
0x4818 FFFF
0x4819 0FFF
0x4819 1FFF
0x4819 2FFF
0x4819 3FFF
0x4819 4FFF
0x4819 5FFF
0x4819 6FFF
0x4819 7FFF
0x4819 8FFF
0x4819 9FFF
0x4819 AFFF
0x4819 BFFF
0x481F FFFF
0x4820 0FFF
0x4823 FFFF
0x4824 0FFF
SIZE
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
400KB
4KB
252KB
4KB
DESCRIPTION
Peripheral Registers
Support Registers
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Peripheral Registers
Support Registers
Peripheral Registers
Support Registers
Reserved
Cortex™-A8 Accessible Only
Cortex™-A8 Accessible Only
Cortex™-A8 Accessible Only
0x4824 1000
0x4828 1000
0x4830 0000
0x4827 FFFF
0x482F FFFF
0x48FF FFFF
252KB
508KB
13MB
Cortex™-A8 Accessible Only
Cortex™-A8 Accessible Only
Reserved
(1) These regions (highlighted in yellow) are decoded internally by the Cortex™-A8 Subsystem and are not physically part of the L4
standard. They are included here only for reference when considering the Cortex™-A8 memory map. For masters other than the
Cortex™-A8, these regions are reserved.
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