TMS320DM8168 Datasheet, PDF (22/312 Pages) Texas Instruments – TMS320DM816x DaVinci Digital Media Processors

TMS320DM8168, TMS320DM8167
TMS320DM8166, TMS320DM8165
SPRS614 – MARCH 2011
HEX ADDRESS
0x4818 0E00
0x4818 0E04
0x4818 0E10
0x4818 0E14
Table 2-21. PRM_IVAHD2 Register Summary
ACRONYM
PM_IVAHD2_PWRSTCTRL
PM_IVAHD2_PWRSTST
RM_IVAHD2_RSTCTRL
RM_IVAHD2_RSTST
REGISTER NAME
HDVICP2-2 power state control
HDVICP2-2 power domain state status
HDVICP2-2 subsystem reset control release
HDVICP2-2 domain reset source log
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HEX ADDRESS
0x4818 0F00
0x4818 0F04
0x4818 0F10
0x4818 0F14
Table 2-22. PRM_SGX Register Summary
ACRONYM
PM_SGX_PWRSTCTRL
RM_SGX_RSTCTRL
PM_SGX_PWRSTST
RM_SGX_RSTST
REGISTER NAME
SGX530 power state control
SGX530 domain reset control release
SGX530 power domain state status
SGX530 domain reset source log
Table 2-23. CM_ALWON Register Summary
HEX ADDRESS
0x4818 1400
0x4818 1404
0x4818 1408
0x4818 140C
0x4818 1410
0x4818 1414
0x4818 1418
0x4818 141C
0x4818 1420
0x4818 1424
0x4818 1428
0x4818 142C
0x4818 1430
0x4818 1540
0x4818 1544
0x4818 1548
0x4818 154C
0x4818 1550
0x4818 1554
0x4818 1558
0x4818 155C
0x4818 1560
0x4818 1564
0x4818 1568
0x4818 1570
0x4818 1574
0x4818 1578
0x4818 157C
0x4818 1580
0x4818 1584
0x4818 1588
0x4818 158C
0x4818 1590
ACRONYM
CM_ALWON_L3_SLOW_CLKSTCTRL
CM_ETHERNET_CLKSTCTRL
CM_ALWON_L3_MED_CLKSTCTRL
CM_MMU_CLKSTCTRL
CM_MMUCFG_CLKSTCTRL
CM_ALWON_OCMC_0_CLKSTCTRL
CM_ALWON_OCMC_1_CLKSTCTRL
CM_ALWON_MPU_CLKSTCTRL
CM_ALWON_SYSCLK4_CLKSTCTRL
CM_ALWON_SYSCLK5_CLKSTCTRL
CM_ALWON_SYSCLK6_CLKSTCTRL
CM_ALWON_RTC_CLKSTCTRL
CM_ALWON_L3_FAST_CLKSTCTRL
CM_ALWON_MCASP0_CLKCTRL
CM_ALWON_MCASP1_CLKCTRL
CM_ALWON_MCASP2_CLKCTRL
CM_ALWON_MCBSP_CLKCTRL
CM_ALWON_UART_0_CLKCTRL
CM_ALWON_UART_1_CLKCTRL
CM_ALWON_UART_2_CLKCTRL
CM_ALWON_GPIO_0_CLKCTRL
CM_ALWON_GPIO_1_CLKCTRL
CM_ALWON_I2C_0_CLKCTRL
CM_ALWON_I2C_1_CLKCTRL
CM_ALWON_TIMER_1_CLKCTRL
CM_ALWON_TIMER_2_CLKCTRL
CM_ALWON_TIMER_3_CLKCTRL
CM_ALWON_TIMER_4_CLKCTRL
CM_ALWON_TIMER_5_CLKCTRL
CM_ALWON_TIMER_6_CLKCTRL
CM_ALWON_TIMER_7_CLKCTRL
CM_ALWON_WDTIMER_CLKCTRL
CM_ALWON_SPI_CLKCTRL
REGISTER NAME
L3 clock domain power state transition
EMAC clock domain power state transition
L3 clock domain power state transition
MMU clock domain power state transition
MMU CFG clock domain power state transition
OCMC 0 clock domain power state transition
OCMC 1 clock domain power state transition
MPU clock domain power state transition
SYSCLK4 clock domain power state transition
SYSCLK5 clock domain power state transition
SYSCLK6 clock domain power state transition
RTC clock domain power state transition
L3 clock domain power state transition
McASP 0 clock management control
McASP 1 clock management control
McASP 2 clock management control
McBSP clock management control
UART 0 clock management control
UART 1 clock management control
UART 2 clock management control
GPIO 0 clock management control
GPIO 1 clock management control
I2C 0 clock management control
I2C 1 clock management control
Timer1 clock management control
Timer2 clock management control
Timer3 clock management control
Timer4 clock management control
Timer5 clock management control
Timer6 clock management control
Timer7 clock management control
WDTIMER clock management control
SPI clock management control
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