TMS320C6472EZTZ7 Datasheet, PDF (64/269 Pages) Texas Instruments – TMS320C6472 Fixed-Point Digital Signal Processor

TMS320C6472
SPRS612G – JUNE 2009 – REVISED JULY 2011
www.ti.com
Table 3-3. Device Control Register (DEVCTL) Field Descriptions (continued)
Bit Field
9 TSIP2_EN[0]
8 TSIP1_EN[2]
7 TSIP1_EN[1]
6 TSIP1_EN[0]
5 TSIP0_EN[2]
4 TSIP0_EN[1]
3 TSIP0_EN[0]
2 UTOPIA_EN[1]
1 UTOPIA_EN[0]
0 HPI_EN
Value
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Description
TSIP2 Internal Pulls Enable[0]. Initialized at reset from GP04/TSIP2_EN pin.
Enable the pulls on all TSIP2 I/O pins and power down the I/O buffers. When this bit is low, the
values of TSIP2_EN[2:1] = don't care.
Disable the pulls on CLKA, CLKB, FSA, FSB, TX[1:0], and TR[1:0] of the TSIP2 I/O pins and power
up the corresponding I/O buffers.
TSIP1 Internal Pulls Enable[2]. Initialized at reset from GP03/TSIP1_EN pin.
Enable the pulls on TX[7:4] and TR[7:4] of the TSIP1 I/O pins and power down the corresponding
I/O buffers.
Disable the pulls on TX[7:4] and TR[7:4] of the TSIP1 I/O pins and power up the corresponding I/O
buffers.
TSIP1 Internal Pulls Enable[1]. Initialized at reset from GP03/TSIP1_EN pin.
Enable the pulls on TX[3:2] and TR[3:2] of the TSIP1 I/O pins and power down the corresponding
I/O buffers.
Disable the pulls on TX[3:2] and TR[3:2] of the TSIP1 I/O pins and power up the corresponding I/O
buffers.
TSIP1 Internal Pulls Enable[0]. Initialized at reset from GP03/TSIP1_EN pin.
Enable the pulls on all TSIP1 I/O pins and power down the I/O buffers. When this bit is low, the
values of TSIP1_EN[2:1] = don't care.
Disable the pulls on CLKA, CLKB, FSA, FSB, TX[1:0], and TR[1:0] of the TSIP1 I/O pins and power
up the corresponding I/O buffers.
TSIP0 Internal Pulls Enable[2]. Initialized at reset from GP02/TSIP0_EN pin.
Enable the pulls on TX[7:4] and TR[7:4] of the TSIP0 I/O pins and power down the corresponding
I/O buffers.
Disable the pulls on TX[7:4] and TR[7:4] of the TSIP0 I/O pins and power up the corresponding I/O
buffers.
TSIP0 Internal Pulls Enable[1]. Initialized at reset from GP02/TSIP0_EN pin.
Enable the pulls on TX[3:2] and TR[3:2] of the TSIP0 I/O pins and power down the corresponding
I/O buffers.
Disable the pulls on TX[3:2] and TR[3:2] of the TSIP0 I/O pins and power up the corresponding I/O
buffers.
TSIP0 Internal Pulls Enable[0]. Initialized at reset from GP02/TSIP0_EN pin.
Enable the pulls on all TSIP0 I/O pins and power down the I/O buffers. When this bit is low, the
values of TSIP0_EN[2:1] = don't care.
Disable the pulls on the clock inputs and control inputs and outputs of the UTOPIA I/O pins and
power up the corresponding I/O buffers.
UTOPIA Internal Pulls Enable[1]. Initialized at reset from GP01/UTOPIA_EN pin.
Enable the pulls on UXDATA[15:8] and URDATA[15:8] of the UTOPIA I/O pins and power down the
corresponding I/O buffers.
Disable the pulls on UXDATA[15:8] and URDATA[15:8] of the UTOPIA I/O pins and power up the
corresponding I/O buffers.
UTOPIA Internal Pulls Enable [0]. Initialized at reset from GP01/UTOPIA_EN pin.
Enable the pulls on all UTOPIA I/O pins and power down the I/O buffers. When this bit is low, the
value of UTOPIA_EN[1] = don't care.
Disable the pulls on the UTOPIA clock inputs, control inputs and outputs, UXDATA[7:0], and
URDATA[7:0] and power up the corresponding I/O buffers.
HPI Internal Pulls Enable. Initialized at reset from GP01/UTOPIA_EN pin.
Enable the pulls on the HPI I/O pins and power down the corresponding I/O buffers.
Disable the pulls on all HPI I/O pins except HAS, HCS, and HINT and power up all HPI I/O buffers.
64
Device Configuration
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