TMS320C6472EZTZ7 Datasheet, PDF (211/269 Pages) Texas Instruments – TMS320C6472 Fixed-Point Digital Signal Processor

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TMS320C6472
SPRS612G – JUNE 2009 – REVISED JULY 2011
Table 7-95. DMATCU Receive Channels 0-5 Registers (continued)
HEX ADDRESS RANGE
0258 1870 - 0258 187C
0258 1880
0258 1884
0258 1888
0258 188C
0258 1890 - 0258 189C
0258 18A0
0258 18A4
0258 18A8
0258 18AC
0258 18B0 - 0258 18BC
0258 18C0
0258 18C4
0258 18C8
0258 18CC
0258 18D0 - 0258 18DC
0258 18E0
0258 18E4
0258 18E8
0258 18EC
0258 18F0 - 0258 18FC
0258 1900
0258 1904
0258 1908
0258 190C
0258 1910 - 0258 191C
0258 1920
0258 1924
0258 1928
0258 192C
0258 1930 - 0258 193C
0258 1940
0258 1944
0258 1948
0258 194C
0258 1950 - 0258 195C
0258 1960
0258 1964
0258 1968
0258 196C
0258 1970 - 0258 197C
ACRONYM
-
DRCH_ABASE2
DRCH_AFALLOC2
DRCH_AFSIZE2
DRCH_AFCNT2
-
DRCH_BBASE2
DRCH_BFALLOC2
DRCH _BFSIZE2
DRCH _BFCNT2
-
DRCH_ABASE3
DRCH_AFALLOC3
DRCH_AFSIZE3
DRCH_AFCNT3
-
DRCH_BBASE3
DRCH_BFALLOC3
DRCH _BFSIZE3
DRCH _BFCNT3
-
DRCH_ABASE4
DRCH_AFALLOC4
DRCH_AFSIZE4
DRCH_AFCNT4
-
DRCH_BBASE4
DRCH_BFALLOC4
DRCH _BFSIZE4
DRCH _BFCNT4
-
DRCH_ABASE5
DRCH_AFALLOC5
DRCH_AFSIZE5
DRCH_AFCNT5
-
DRCH_BBASE5
DRCH_BFALLOC5
DRCH _BFSIZE5
DRCH _BFCNT5
-
REGISTER NAME
Reserved
Receive Channel 2 Memory Base Address Register A
Receive Channel 2 Frame Allocation Register A
Receive Channel 2 Frame Size Register A
Receive Channel 2 Frame Count Register A
Reserved
Receive Channel 2 Memory Base Address Register B
Receive Channel 2 Frame Allocation Register B
Receive Channel 2 Frame Size Register B
Receive Channel 2 Frame Count Register B
Reserved
Receive Channel 3 Memory Base Address Register A
Receive Channel 3 Frame Allocation Register A
Receive Channel 3 Frame Size Register A
Receive Channel 3 Frame Count Register A
Reserved
Receive Channel 3 Memory Base Address Register B
Receive Channel 3 Frame Allocation Register B
Receive Channel 3 Frame Size Register B
Receive Channel 3 Frame Count Register B
Reserved
Receive Channel 4 Memory Base Address Register A
Receive Channel 4 Frame Allocation Register A
Receive Channel 4 Frame Size Register A
Receive Channel 4 Frame Count Register A
Reserved
Receive Channel 4 Memory Base Address Register B
Receive Channel 4 Frame Allocation Register B
Receive Channel 4 Frame Size Register B
Receive Channel 4 Frame Count Register B
Reserved
Receive Channel 5 Memory Base Address Register A
Receive Channel 5 Frame Allocation Register A
Receive Channel 5 Frame Size Register A
Receive Channel 5 Frame Count Register A
Reserved
Receive Channel 5 Memory Base Address Register B
Receive Channel 5 Frame Allocation Register B
Receive Channel 5 Frame Size Register B
Receive Channel 5 Frame Count Register B
Reserved
HEX ADDRESS RANGE
0258 8000 - 0258 80FC
0258 8100 - 0258 81FC
0258 8200 - 0258 82FC
Table 7-96. TDMU Channel Bitmaps
ACRONYM
XBM_XBMA0
XBM_XBMB0
XBM_XBMA1
REGISTER NAME
Transmit Channel 0 Bitmap A
Transmit Channel 0 Bitmap B
Transmit Channel 1 Bitmap A
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C64x+ Peripheral Information and Electrical Specifications 211
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