TMS320C6472EZTZ7 Datasheet, PDF (124/269 Pages) Texas Instruments – TMS320C6472 Fixed-Point Digital Signal Processor

TMS320C6472
SPRS612G – JUNE 2009 – REVISED JULY 2011
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7.5 Enhanced Direct Memory Access (EDMA3) Controller
The primary purpose of the EDMA3 is to service user-programmed data transfers between two
memory-mapped slave endpoints on the device. The EDMA3 services software-driven paging transfers
(e.g., data movement between external memory and internal memory), performs sorting or subframe
extraction of various data structures and offloads data transfers from the device CPU.
The EDMA3 includes the following features:
• Fully orthogonal transfer description
– 3 transfer dimensions: array (multiple bytes), frame (multiple arrays), and block (multiple frames)
– Single event can trigger transfer of array, frame, or entire block
– Independent indexes on source and destination
• Flexible transfer definition:
– Increment or FIFO transfer addressing modes
– Linking mechanism allows for ping-pong buffering, circular buffering, and repetitive/continuous
transfers, all with no CPU intervention
– Chaining allows multiple transfers to execute with one event
• 256 PaRAM entries
– Used to define transfer context for channels
– Each PaRAM entry can be used as a DMA entry, QDMA entry, or link entry
• 64 DMA channels
– Manually triggered (CPU writes to channel controller register), external event triggered, and chain
triggered (completion of one transfer triggers another)
• 4 Quick DMA (QDMA) channels
– Used for software-driven transfers
– Triggered upon writing to a single PaRAM set entry
• 4 transfer controllers/event queues with programmable system-level priority
• Interrupt generation for transfer completion and error conditions
• Debug visibility
– Queue watermarking/threshold allows detection of maximum usage of event queues
– Error and status recording to facilitate debug
Each of the transfer controllers has a direct connection to the switched central resource (SCR). Table 4-1
lists the peripherals that can be accessed by the transfer controllers.
7.5.1 EDMA3 Channel Synchronization Events
The C64x+ EDMA3 supports up to 64 EDMA channels which service peripheral devices and external
memory. Table 7-4 lists the source of C64x+ EDMA3 synchronization events associated with each of the
programmable EDMA channels. For the C6472 device, the association of an event to a channel is fixed;
each of the EDMA channels has one specific event associated with it. These specific events are captured
in the EDMA event registers (ERL, ERH) even if the events are disabled by the EDMA event enable
registers (EERL, EERH). The priority of each event can be specified independently in the transfer
parameters stored in the EDMA parameter RAM. For more detailed information on the EDMA module and
how EDMA events are enabled, captured, processed, linked, chained, and cleared, etc., see the
TMS320C6472/TMS320TCI648x DSP Enhanced DMA (EDMA3) Controller User's Guide (literature
number SPRU727).
124 C64x+ Peripheral Information and Electrical Specifications
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