OMAP3530_15 Datasheet, PDF (62/265 Pages) Texas Instruments – OMAP3530 and OMAP3525 Applications Processors

OMAP3530, OMAP3525
SPRS507H – FEBRUARY 2008 – REVISED OCTOBER 2013
www.ti.com
Table 2-2. Ball Characteristics (CBC Pkg.)⁽¹⁾ (continued)
BALL
BALL TOP PIN NAME
BOTTOM [1]
[2]
[3]
MODE [4]
safe_mode
7
H25
NA
dss_data7
0
uart1_rx
2
gpio_77
4
hw_dbg15
5
safe_mode
7
H26
NA
dss_data8
0
gpio_78
4
hw_dbg16
5
safe_mode
7
J26
NA
dss_data9
0
gpio_79
4
hw_dbg17
5
safe_mode
7
L25
NA
dss_data16
0
gpio_86
4
safe_mode
7
L26
NA
dss_data17
0
gpio_87
4
safe_mode
7
M24
NA
dss_data18
0
mcspi3_clk
2
dss_data0
3
gpio_88
4
safe_mode
7
M26
NA
dss_data19
0
mcspi3_simo
2
dss_data1
3
gpio_89
4
safe_mode
7
N24
NA
dss_data21
0
mcspi3_cs0
2
dss_data3
3
gpio_91
4
safe_mode
7
K24
NA
dss_hsync
0
gpio_67
4
hw_dbg13
5
safe_mode
7
M25
NA
dss_vsync
0
gpio_68
4
safe_mode
7
R8
NA
mcspi1_cs1
0
mmc3_cmd
3
gpio_175
4
safe_mode
7
TYPE [5]
-
IO
I
IO
O
-
IO
IO
O
-
IO
IO
O
-
IO
IO
-
IO
IO
-
IO
IO
IO
IO
-
IO
IO
IO
IO
-
O
IO
IO
IO
-
O
IO
O
-
O
IO
-
O
IO
IO
-
BALL
RESET
STATE [6]
BALL
RESET REL.
STATE [7]
RESET REL.
MODE [8]
POWER [9]
HYS [10]
BUFFER PULLUP
STRENG TH /DOWN IO CELL [13]
(mA) [11] TYPE [12]
L
L
7
vdds
Yes
8
PU100/
LVCMOS
PD100
L
L
7
vdds
Yes
8
PU100/
LVCMOS
PD100
L
L
7
vdds
Yes
8
PU100/
LVCMOS
PD100
L
L
7
vdds
Yes
8
PU100/
LVCMOS
PD100
L
L
7
vdds
Yes
8
PU100/
LVCMOS
PD100
L
L
7
vdds
Yes
8
PU100/
LVCMOS
PD100
L
L
7
vdds
Yes
8
PU100/
LVCMOS
PD100
L
L
7
vdds
Yes
8
PU100/
LVCMOS
PD100
H
H
7
vdds
Yes
4
PU100/
LVCMOS
PD100
H
H
7
vdds
Yes
4
PU100/
LVCMOS
PD100
H
H
7
vdds
Yes
4 ⁽¹⁷⁾
PU100/
LVCMOS
PD100
(17) The buffer strength of this IO cell is programmable (2, 4, 6, or 8 mA) according to the selected mode; the default value is described in
the above table.
62
TERMINAL DESCRIPTION
Copyright © 2008–2013, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: OMAP3530 OMAP3525