OMAP3530_15 Datasheet, PDF (241/265 Pages) Texas Instruments – OMAP3530 and OMAP3525 Applications Processors

OMAP3530, OMAP3525
www.ti.com
SPRS507H – FEBRUARY 2008 – REVISED OCTOBER 2013
Table 6-128. MMC/SD/SDIO Timing Requirements – Standard MMC Mode and MMC Identification Mode⁽¹⁾
(2)
NO.
PARAMETER
1.15 V
1.0 V
MIN
MAX
MIN
MAX
Standard MMC Mode and MMC Identification Mode
MMC/SD/SDIO Interface 1 (1.8 V IO)
MMC3 t_{su(CMDV-CLKIH)}
Setup time, mmc1_cmd valid before
mmc1_clk rising clock edge
13.6
65.7
MMC4 t_{su(CLKIH-CMDIV)}
Hold time, mmc1_cmd valid after mmc1_clk
8.9
8.9
rising clock edge
MMC7 t_{su(DATxV-CLKIH)}
Setup time, mmc1_datx valid before
mmc1_clk rising clock edge
13.6
65.7
MMC8 t_{su(CLKIH-DATxIV)} Hold time, mmc1_datx valid after mmc1_clk
8.9
8.9
rising clock edge
MMC/SD/SDIO Interface 1 (3.0 V IO)
MMC3 t_{su(CMDV-CLKIH)}
Setup time, mmc1_cmd valid before
mmc1_clk rising clock edge
13.6
65.7
MMC4 t_{su(CLKIH-CMDIV)}
Hold time, mmc1_cmd valid after mmc1_clk
8.9
8.9
rising clock edge
MMC7 t_{su(DATxV-CLKIH)}
Setup time, mmc1_datx valid before
mmc1_clk rising clock edge
13.6
65.7
MMC8 t_{su(CLKIH-DATxIV)} Hold time, mmc1_datx valid after mmc1_clk
8.9
8.9
rising clock edge
MMC/SD/SDIO Interface 2
MMC3 t_{su(CMDV-CLKIH)}
Setup time, mmc2_cmd valid before
mmc2_clk rising clock edge
13.6
65.7
MMC4 t_{su(CLKIH-CMDIV)}
Hold time, mmc2_cmd valid after mmc2_clk
8.9
8.9
rising clock edge
MMC7 t_{su(DATxV-CLKIH)}
Setup time, mmc2_datx valid before
mmc2_clk rising clock edge
13.6
65.7
MMC8 t_{su(CLKIH-DATxIV)} Hold time, mmc2_datx valid after mmc2_clk
8.9
8.9
rising clock edge
MMC/SD/SDIO Interface 3
MMC3 t_{su(CMDV-CLKIH)}
Setup time, mmc3_cmd valid before
mmc3_clk rising clock edge
13.6
65.7
MMC4 t_{su(CLKIH-CMDIV)}
Hold time, mmc3_cmd valid after mmc3_clk
8.9
8.9
rising clock edge
MMC7 t_{su(DATxV-CLKIH)}
Setup time, mmc3_datx valid before
mmc3_clk rising clock edge
13.6
65.7
MMC8 t_{su(CLKIH-DATxIV)} Hold time, mmc3_datx valid after mmc3_clk
8.9
8.9
rising clock edge
(1) Timing parameters are referred to output clock specified in Table 6-129.
(2) The timing requirements are assured for the cycle jitter and duty cycle error conditions specified in Table 6-129.
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Table 6-129. MMC/SD/SDIO Switching Characteristics – Standard MMC Mode and MMC Identification
Mode
NO.
PARAMETER
MMC Identification Mode
1/MMC 1/t_c(clk)
1
Frequency⁽¹⁾, mmcx_ clk ⁽²⁾
MMC2 t_W(clkH)
Typical pulse duration, output clk high
1.15 V
MIN
MAX
1.0 V
MIN
MAX
0.4
0.4
X ⁽³⁾*PO ⁽⁴⁾
X ⁽³⁾*PO ⁽⁴⁾
UNIT
MHz
ns
(1) Related with the output clk maximum and minimum frequencies programmable in I/F module.
(2) In mmcx_clk, 'x' is equal to 1, 2, or 3.
(3) The X parameter is defined as shown in Table 6-130.
(4) PO = output clk period in ns.
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TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 241
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