OMAP3530_15 Datasheet, PDF (253/265 Pages) Texas Instruments – OMAP3530 and OMAP3525 Applications Processors

OMAP3530, OMAP3525
www.ti.com
SPRS507H – FEBRUARY 2008 – REVISED OCTOBER 2013
Table 6-149. JTAG Switching Characteristics – Free Running Clock Mode
NO.
PARAMETER
1.15 V
JT1
JT2
JT3
JT11
JT14
t_c(rtck)
t_w(rtckL)
t_w(rtckH)
t_dc(rtck)
t_j(rtck)
t_R(rtck)
t_F(rtck)
t_{d(rtckL-tdoV)}
t_R(tdo)
t_F(tdo)
t_{d(rtckH-emuxV)}
t_R(emux)
t_F(emux)
Cycle time⁽¹⁾, jtag_rtck period
Typical pulse duration, jtag_rtck low
Typical pulse duration, jtag_rtck high
Duty cycle error, jtag_rtck
Jitter standard deviation⁽³⁾, jtag_rtck
Rise time, jtag_rtck
Fall time, jtag_rtck
Delay time, jtag_rtck low to jtag_tdo valid
Rise time, jtag_tdo
Fall time, jtag_tdo
Delay time, jtag_rtck high to ,jtag_emux⁽⁴⁾ valid
Rise time, jtag_emux⁽⁴⁾
Fall time, jtag_emux⁽⁴⁾
MIN
MAX
25
0.5*PO ⁽²⁾
0.5*PO ⁽²⁾
–1250
1250
33.3
4
4
–5.8
5.8
4
4
2.7
15.1
6
6
(1) Related with the jtag_rtck maximum frequency.
(2) PO = jtag _rtck period in ns.
(3) The jitter probability density can be approximated by a Gaussian function.
(4) x = 0 to 1
1.0 V
MIN
MAX
33
0.5*PO ⁽²⁾
0.5*PO ⁽²⁾
–1667
1667
33.3
4
4
–7.9
7.9
4
4
2.7
20.4
6
6
UNIT
ns
ns
ns
ps
ps
ns
ns
ns
ns
ns
ns
ns
ns
jtag_tck
jtag_rtck
jtag_tdi
jtag_tms
jtag_emux(IN)
jtag_tdo
jtag_emux(OUT)
JT4
JT5
JT6
JT1
JT2
JT3
JT7
JT8
JT9
JT10
JT12
JT13
JT11
JT14
In jtag_emux, x is equal to 0 to 1.
Figure 6-72. JTAG Interface Timing – Free Running Clock Mode
030-113
6.8.3.2 JTAG – Adaptive Clock Mode
Table 6-151 and Table 6-152 assume testing over the recommended operating conditions and electrical
characteristic conditions (see Figure 6-73):
Table 6-150. JTAG Timing Conditions – Adaptive Clock Mode
Input Conditions
t_R
t_F
TIMING CONDITION PARAMETER
Input signal rise time
Input signal fall time
VALUE
5
5
UNIT
ns
ns
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TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 253
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