OMAP3530_15 Datasheet, PDF (197/265 Pages) Texas Instruments – OMAP3530 and OMAP3525 Applications Processors

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OMAP3530, OMAP3525
SPRS507H – FEBRUARY 2008 – REVISED OCTOBER 2013
dss_pclk
dss_vsync
dss_hsync
dss_acbias
dss_data[23:0]
DL5
DL4
DL1
DL0
DL2
DL3
030-061
Figure 6-28. LCD Display in TFT Mode – HDTV Application(1) (2) (3) (4)
(1) The pixel data bus depends on the use of 8-, 9-, 12-, 16-, 18-, or 24-bit per pixel data output pins.
(2) The pixel clock frequency is programmable.
(3) All timings not illustrated in the waveform are programmable by software, control signal polarity, and driven edge of dss_pclk.
(4) For more information, see the DSS chapter in the OMAP35x Technical Reference Manual (TRM) [literature number SPRUF98].
6.5.2.1.2 LCD Display in STN Mode
Table 6-38 assumes testing over the recommended operating conditions (see Figure 6-29).
Table 6-38. LCD Display Switching Characteristics in STN Mode^{(3) (4) (5)}
NO.
PARAMETER
OPP3
OPP2
UNIT
MIN
MAX
MIN
MAX
DL3
DL4
DL5
t_{d(PCLKA-DATAV)}
t_c(PCLK)
t_w(PCLK)
Delay time, dss_pclk active edge to dss_data –6.9
6.9
–6.9
6.9
ns
bus valid
Cycle time⁽²⁾, dss_pclk
22.727
22.727
ns
Pulse duration, dss_pclk low or high
0.45*P⁽¹⁾ 0.55*P⁽¹⁾ 0.45*P⁽¹⁾ 0.55*P⁽¹⁾
ns
(1) P = dss_pclk period.
(2) The pixel clock frequency is software programmable via the pixel clock divider configuration from 1 to 255 division range in the
DISPC_DIVISOR register.
(3) The DSS in STN mode is used with 4 or 8 pins only; unused pixel data bits always remain low.
(4) The capacitive load is equivalent to 40 pF.
(5) For more information, see the DSS chapter in the OMAP35x Technical Reference Manual (TRM) [literature number SPRUF98].
Copyright © 2008–2013, Texas Instruments Incorporated
TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 197
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