CC3220 Datasheet, PDF (62/84 Pages) Texas Instruments – SimpleLink Wi-Fi Wireless and Internet-of-Things Solution, a Single-Chip Wireless MCU

CC3220
SWAS035A – SEPTEMBER 2016 – REVISED FEBRUARY 2017
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5.8.2 Internal Memory
The CC3220x device includes on-chip SRAM to which application programs are downloaded and
executed. The application developer must share the SRAM for code and data. The micro direct memory
access (μDMA) controller can transfer data to and from SRAM and various peripherals. The CC3220x
ROM holds the rich set of peripheral drivers, which saves SRAM space. For more information on drivers,
see the CC3220x API list.
5.8.2.1 SRAM
The CC3220x family provides 256KB of on-chip SRAM. Internal RAM is capable of selective retention
during LPDS mode. This internal SRAM is at offset 0x2000 0000 of the device memory map.
Use the µDMA controller to transfer data to and from the SRAM.
When the device enters low-power mode, the application developer can choose to retain a section of
memory based on need. Retaining the memory during low-power mode provides a faster wakeup. The
application developer can choose the amount of memory to retain in multiples of 64KB. For more
information, see the API guide.
5.8.2.2 ROM
The internal zero-wait-state ROM of the CC3220x device is at address 0x0000 0000 of the device memory
and is programmed with the following components:
• Bootloader
• Peripheral driver library (DriverLib) release for product-specific peripherals and interfaces
The bootloader is used as an initial program loader (when the serial flash memory is empty). The
CC3220x DriverLib software library controls on-chip peripherals with a bootloader capability. The library
performs peripheral initialization and control functions, with a choice of polled or interrupt-driven peripheral
support. The DriverLib APIs in ROM can be called by applications to reduce flash memory requirements
and free the flash memory for other purposes.
5.8.2.3 Flash Memory
The CC3220SF device comes with an on-chip flash memory of 1MB that allows application code to
execute in place while freeing SRAM exclusively for read-write data. The flash memory is used for code
and constant data sections and is directly attached to the ICODE/DCODE bus of the Cortex-M4 core. A
128-bit-wide instruction prefetch buffer allows maintenance of maximum performance for linear code or
loops that fit inside the buffer.
The flash memory is organized as 2-KB sectors that can be independently erased. Reads and writes can
be performed at word (32-bit) level.
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