CC3220 Datasheet, PDF (52/84 Pages) Texas Instruments – SimpleLink Wi-Fi Wireless and Internet-of-Things Solution, a Single-Chip Wireless MCU

CC3220
SWAS035A – SEPTEMBER 2016 – REVISED FEBRUARY 2017
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5.3 ARM^® Cortex^®-M4 Processor Core Subsystem
The high-performance Cortex-M4 processor provides a low-cost platform that meets the needs of minimal
memory implementation, reduced pin count, and low power consumption, while delivering outstanding
computational performance and exceptional system response to interrupts.
• The Cortex-M4 core has low-latency interrupt processing with the following features:
– A 32-bit ARM^® Thumb^® instruction set optimized for embedded applications
– Handler and thread modes
– Low-latency interrupt handling by automatic processor state saving and restoration during entry and
exit
– Support for ARMv6 unaligned accesses
• Nested vectored interrupt controller (NVIC) closely integrated with the processor core to achieve low-
latency interrupt processing. The NVIC includes the following features:
– Bits of priority configurable from 3 to 8
– Dynamic reprioritization of interrupts
– Priority grouping that enables selection of preempting interrupt levels and nonpreempting interrupt
levels
– Support for tail-chaining and late arrival of interrupts, which enables back-to-back interrupt
processing without the overhead of state saving and restoration between interrupts
– Processor state automatically saved on interrupt entry and restored on interrupt exit with no
instruction overhead
– Wake-up interrupt controller (WIC) providing ultra-low-power sleep mode support
• Bus interfaces:
– Advanced high-performance bus (AHB-Lite) interfaces: system bus interfaces
– Bit-band support for memory and select peripheral that includes atomic bit-band write and read
operations
• Low-cost debug solution featuring:
– Debug access to all memory and registers in the system, including access to memory-mapped
devices, access to internal core registers when the core is halted, and access to debug control
registers even while SYSRESETn is asserted
– Serial wire debug port (SW-DP) or serial wire JTAG debug port (SWJ-DP) debug access
– Flash patch and breakpoint (FPB) unit to implement breakpoints and code patches
5.4 Wi-Fi Network Processor Subsystem
The Wi-Fi network processor subsystem includes a dedicated ARM MCU to completely offload the host
MCU along with an 802.11 b/g/n radio, baseband, and MAC with a powerful crypto engine for a fast,
secure WLAN and Internet connections with 256-bit encryption. The CC3220x devices support station, AP,
and Wi-Fi Direct modes. The device also supports WPA2 personal and enterprise security and WPS 2.0.
The Wi-Fi network processor includes an embedded IPv6, IPv4 TCP/IP stack.
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