CC3220 Datasheet, PDF (23/84 Pages) Texas Instruments – SimpleLink Wi-Fi Wireless and Internet-of-Things Solution, a Single-Chip Wireless MCU

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CC3220
SWAS035A – SEPTEMBER 2016 – REVISED FEBRUARY 2017
3.3 Drive Strength and Reset States for Analog and Digital Multiplexed Pins
Table 3-2 describes the use, drive strength, and default state of analog and digital multiplexed pins at first-
time power up and reset (nRESET pulled low).
Table 3-2. Drive Strength and Reset States for Analog and Digital Multiplexed Pins
State After Configuration of
Pin
Board-Level Configuration Default State at First Power Analog Switches (ACTIVE, Maximum Effective Drive
and Use
Up or Forced Reset
LPDS, and HIB Power
Strength (mA)
Modes)
Connected to the enable pin
29
of the RF switch (ANTSEL1). Analog is isolated. The digital Determined by the I/O state,
Other use is not
I/O cell is also isolated.
as are other digital I/Os.
4
recommended.
Connected to the enable pin
30
of the RF switch (ANTSEL2). Analog is isolated. The digital Determined by the I/O state,
Other use is not
I/O cell is also isolated.
as are other digital I/Os.
4
recommended.
VDD_ANA2 (pin 47) must be
45
shorted to the input supply
rail. Otherwise, the pin is
Analog is isolated. The digital Determined by the I/O state,
I/O cell is also isolated.
as are other digital I/Os.
4
driven by the ANA2 DC-DC.
50
Generic I/O
Analog is isolated. The digital Determined by the I/O state,
I/O cell is also isolated.
as are other digital I/Os.
4
The pin must have an
52
external pullup of 100 kΩ to Analog is isolated. The digital Determined by the I/O state,
the supply rail and must be I/O cell is also isolated.
as are other digital I/Os.
4
used in output signals only.
53
Generic I/O
Analog is isolated. The digital Determined by the I/O state,
I/O cell is also isolated.
as are other digital I/Os.
4
57
Analog signal (1.8-V
absolute, 1.46-V full scale)
ADC is isolated. The digital Determined by the I/O state,
I/O cell is also isolated.
as are other digital I/Os.
4
58
Analog signal (1.8-V
absolute, 1.46-V full scale)
ADC is isolated. The digital Determined by the I/O state,
I/O cell is also isolated.
as are other digital I/Os.
4
59
Analog signal (1.8-V
absolute, 1.46-V full scale)
ADC is isolated. The digital Determined by the I/O state,
I/O cell is also isolated.
as are other digital I/Os.
4
60
Analog signal (1.8-V
absolute, 1.46-V full scale)
ADC is isolated. The digital Determined by the I/O state,
I/O cell is also isolated.
as are other digital I/Os.
4
3.4 Pad State After Application of Power To Chip But Before Reset Release
When a stable power is applied to the CC3220x chip for the first time or when supply voltage is restored
to the proper value following a period with supply voltage less than 1.5 V, the level of each digital pad is
undefined in the period starting from the release of nRESET and until DIG_DCDC powers up. This period
is less than approximately 10 ms. During this period, pads can be internally pulled weakly in either
direction. If a certain set of pins is required to have a definite value during this prereset period, an
appropriate pullup or pulldown resistor must be used at the board level. The recommended value of this
external pull is 2.7 kΩ.
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