MSP430FR59691 Datasheet, PDF (61/131 Pages) Texas Instruments – MSP430FR59xx Mixed-Signal Microcontrollers

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MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967
MSP430FR5959, MSP430FR5958, MSP430FR5957
MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471
SLAS704C – OCTOBER 2012 – REVISED JUNE 2014
Table 6-9. System Module Interrupt Vector Registers (continued)
INTERRUPT VECTOR
REGISTER
SYSSNIV, System NMI
SYSUNIV, User NMI
ADDRESS
019Ch
019Ah
INTERRUPT EVENT
VALUE PRIORITY
FRCTLPW password violation (PUC)
Uncorrectable FRAM bit error detection (PUC)
Peripheral area fetch (PUC)
PMMPW PMM password violation (PUC)
MPUPW MPU password violation (PUC)
CSPW CS password violation (PUC)
MPUSEGPIFG encapsulated IP memory segment violation
(PUC)
MPUSEGIIFG information memory segment violation (PUC)
MPUSEG1IFG segment 1 memory violation (PUC)
MPUSEG2IFG segment 2 memory violation (PUC)
MPUSEG3IFG segment 3 memory violation (PUC)
ACCTEIFG access time error (PUC) ⁽¹⁾
Reserved
No interrupt pending
SVS low-power reset entry
Uncorrectable FRAM bit error detection
Reserved
MPUSEGPIFG encapsulated IP memory segment violation
MPUSEGIIFG information memory segment violation
MPUSEG1IFG segment 1 memory violation
MPUSEG2IFG segment 2 memory violation
MPUSEG3IFG segment 3 memory violation
VMAIFG Vacant memory access
JMBINIFG JTAG mailbox input
JMBOUTIFG JTAG mailbox output
Correctable FRAM bit error detection
Reserved
No interrupt pending
NMIFG NMI pin
OFIFG oscillator fault
Reserved
Reserved
Reserved
1Ah
1Ch
1Eh
20h
22h
24h
26h
28h
2Ah
2Ch
2Eh
30h
32h to 3Eh
00h
02h
04h
06h
08h
0Ah
0Ch
0Eh
10h
12h
14h
16h
18h
1Ah to
1Eh
00h
02h
04h
06h
08h
0Ah to
1Eh
Lowest
Highest
Lowest
Highest
Lowest
(1) Indicates incorrect wait state settings.
6.10.8 DMA Controller
The DMA controller allows movement of data from one memory address to another without CPU
intervention. For example, the DMA controller can be used to move data from the ADC12_B conversion
memory to RAM. Using the DMA controller can increase the throughput of peripheral modules. The DMA
controller reduces system power consumption by allowing the CPU to remain in sleep mode, without
having to awaken to move data to or from a peripheral.
Copyright © 2012–2014, Texas Instruments Incorporated
Detailed Description
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