MSP430FR59691 Datasheet, PDF (17/131 Pages) Texas Instruments – MSP430FR59xx Mixed-Signal Microcontrollers

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MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967
MSP430FR5959, MSP430FR5958, MSP430FR5957
MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471
SLAS704C – OCTOBER 2012 – REVISED JUNE 2014
5 Specifications
5.1 Absolute Maximum Ratings⁽¹⁾
over operating free-air temperature range (unless otherwise noted)
Voltage applied at DVCC and AVCC pins to V_SS
Voltage difference between DVCC and AVCC pins⁽²⁾
Voltage applied to any pin ⁽³⁾
Diode current at any device pin
–0.3 V to 4.1 V
±0.3V
–0.3 V to (V_CC + 0.3 V),
4.1 V Max
±2 mA
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Voltage differences between DVCC and AVCC exceeding the specified limits may cause malfunction of the device including erroneous
writes to RAM and FRAM.
(3) All voltages referenced to V_SS.
5.2 Handling Ratings
MIN
MAX
UNIT
T_stg
Storage temperature range⁽¹⁾
-40
125
°C
(1) Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.
5.3 Recommended Operating Conditions
Typical data are based on V_CC = 3.0 V, T_A = 25°C, unless otherwise noted
MIN NOM MAX UNIT
V_CC
Supply voltage range applied at all DVCC and AVCC
pins ^{(1) (2) (3)}
1.8 ⁽⁴⁾
3.6 V
V_SS
T_A
C_DVCC
f_SYSTEM
Supply voltage applied at all DVSS and AVSS pins
Operating free-air temperature
Capacitor value at DVCC⁽⁵⁾
Processor frequency (maximum MCLK frequency)⁽⁶⁾
No FRAM wait states
(NWAITSx = 0)
With FRAM wait states
(NWAITSx = 1)⁽⁸⁾
-40
1_-20%
0
0
0
V
85 °C
µF
8 ⁽⁷⁾
16 ⁽⁹⁾
MHz
f_ACLK
f_SMCLK
Maximum ACLK frequency
Maximum SMCLK frequency
50 kHz
16⁽⁹⁾ MHz
(1) It is recommended to power AVCC and DVCC pins from the same source. At a minimum, during power up, power down, and device
operation, the voltage difference between AVCC and DVCC must not exceed the limits specified in Absolute Maximum Ratings.
Exceeding the specified limits may cause malfunction of the device including erroneous writes to RAM and FRAM.
(2) See Table 5-1 for additional important information.
(3) Modules may have a different supply voltage range specification. Refer to the specification of the respective module in this data sheet.
(4) The minimum supply voltage is defined by the supervisor SVS levels. See Table 5-2 for the exact values.
(5) Connect a low-ESR capacitor with at least the value specified and a maximum tolerance of 20% as close as possible to the DVCC pin.
(6) Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet.
(7) DCO settings and HF crystals with a typical value less or equal the specified MAX value are permitted.
(8) Wait states only occur on actual FRAM accesses; that is, on FRAM cache misses. RAM and peripheral accesses are always executed
without wait states.
(9) DCO settings and HF crystals with a typical value less than or equal to the specified MAX value are permitted. If a clock source with a
higher typical value is used, the clock must be divided in the clock system.
Copyright © 2012–2014, Texas Instruments Incorporated
Specifications
17
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MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471