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MSP430F530X_12 Datasheet, PDF (60/100 Pages) Texas Instruments – MIXED SIGNAL MICROCONTROLLER
MSP430F530x, MSP430F5310
SLAS677C – SEPTEMBER 2010 – REVISED SEPTEMBER 2012
www.ti.com
10-Bit ADC, Power Supply and Input Range Conditions
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
AVCC
V(Ax)
PARAMETER
TEST CONDITIONS
VCC
Analog supply voltage
AVCC and DVCC are connected together,
AVSS and DVSS are connected together,
V(AVSS) = V(DVSS) = 0 V
Analog input voltage range (2)
All ADC10_A pins: P1.0 to P1.5 and P3.6 and
P3.7 terminals
MIN TYP MAX UNIT
1.8
3.6 V
0
AVCC V
Operating supply current into
AVCC terminal. REF module
and reference buffer off.
fADC10CLK = 5 MHz, ADC10ON = 1, REFON =
0,
SHT0 = 0, SHT1 = 0, ADC10DIV = 0,
ADC10SREF = 00
2.2 V
3V
60 100
µA
75 110
Operating supply current into
AVCC terminal. REF module
on, reference buffer on.
fADC10CLK = 5 MHz, ADC10ON = 1, REFON =
1,
SHT0 = 0, SHT1 = 0, ADC10DIV = 0,
ADC10SREF = 01
3V
IADC10_A
Operating supply current into
AVCC terminal. REF module
off, reference buffer on.
fADC10CLK = 5 MHz, ADC10ON = 1, REFON =
0,
SHT0 = 0, SHT1 = 0, ADC10DIV = 0,
ADC10SREF = 10, VEREF = 2.5 V
3V
113 150 µA
105 140 µA
Operating supply current into
AVCC terminal. REF module
off, reference buffer off.
fADC10CLK = 5 MHz, ADC10ON = 1, REFON =
0,
SHT0 = 0, SHT1 = 0, ADC10DIV = 0,
ADC10SREF = 11, VEREF = 2.5 V
3V
70 110 µA
CI
Input capacitance
Only one terminal Ax can be selected at one
time from the pad to the ADC10_A capacitor
array including wiring and pad.
2.2 V
3.5
pF
RI
Input MUX ON resistance
AVCC > 2.0 V, 0 V ≤ VAx ≤ AVCC
1.8 V < AVCC < 2.0 V, 0 V ≤ VAx ≤ AVCC
36
kΩ
96
(1) The leakage current is defined in the leakage current table with P6.x/Ax parameter.
(2) The analog input voltage range must be within the selected reference voltage range VR+ to VR– for valid conversion results. The external
reference voltage requires decoupling capacitors. See ().
10-Bit ADC, Timing Parameters
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
fADC10CLK
TEST CONDITIONS
For specified performance of ADC10_A linearity
parameters
VCC
2.2 V, 3 V
MIN TYP
0.45
5
fADC10OSC
Internal ADC10_A
oscillator (1)
ADC10DIV = 0, fADC10CLK = fADC10OSC
2.2 V, 3 V
4.2 4.8
tCONVERT Conversion time
REFON = 0, Internal oscillator, 12 ADC10CLK
cycles, 10-bit mode
fADC10OSC = 4 MHz to 5 MHz
2.2 V, 3 V
2.4
External fADC10CLK from ACLK, MCLK or SMCLK,
(2)
ADC10SSEL ≠ 0
tADC10ON
tSample
Turn on settling time of
the ADC
Sampling time
See (3)
RS = 1000 Ω, RI = 96 kΩ, CI = 3.5 pF (4)
RS = 1000 Ω, RI = 36 kΩ, CI = 3.5 pF (4)
1.8 V
3
3V
1
MAX UNIT
5.5 MHz
5.4 MHz
3.0
µs
100 ns
µs
µs
(1) The ADC10OSC is sourced directly from MODOSC inside the UCS.
(2) 12 × ADC10DIV × 1/fADC10CLK
(3) The condition is that the error in a conversion started after tADC10ON is less than ±0.5 LSB. The reference and input signal are already
settled.
(4) Approximately eight Tau (τ) are needed to get an error of less than ±0.5 LSB
60
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