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TCA9548A_15 Datasheet, PDF (6/35 Pages) Texas Instruments – Low-Voltage 8-Channel I2C Switch With Reset
TCA9548A
SCPS207E – MAY 2012 – REVISED OCTOBER 2015
www.ti.com
Electrical Characteristics(1) (continued)
VCC = 2.3 V to 3.6 V, over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN TYP(2)
RON
Switch-on resistance
VO = 0.4 V, IO = 15 mA
VO = 0.4 V, IO = 10 mA
4.5 V to 5.5 V
3 V to 3.6 V
2.3 V to 2.7 V
1.65 V to 1.95 V
4
10
5
12
7
15
10
25
MAX
20
30
45
70
UNIT
Ω
6.6 I2C Interface Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 5)
STANDARD MODE
I2C BUS
FAST MODE
I2C BUS
fscl
tsch
tscl
tsp
tsds
tsdh
ticr
ticf
tocf
tbuf
tsts
tsth
tsps
tvdL(Data)
tvdH(Data)
tvd(ack)
Cb
I2C clock frequency
I2C clock high time
I2C clock low time
I2C spike time
I2C serial-data setup time
I2C serial-data hold time
I2C input rise time
I2C input fall time
I2C output (SDn) fall time (10-pF to 400-pF bus)
I2C bus free time between stop and start
I2C start or repeated start condition setup
I2C start or repeated start condition hold
I2C stop condition setup
Valid-data time (high to low)(3) SCL low to SDA output low valid
Valid-data time (low to high)(3) SCL low to SDA output high valid
Valid-data time of ACK condition
I2C bus capacitive load
ACK signal from SCL low
to SDA output low
MIN
MAX
MIN MAX
0
100
0
400
4
0.6
4.7
1.3
50
50
250
100
0 (1)
0 (1)
1000 20 + 0.1Cb (2)
300
300 20 + 0.1Cb (2)
300
300 20 + 0.1Cb (2)
300
4.7
1.3
4.7
0.6
4
0.6
4
0.6
1
1
0.6
0.6
1
1
400
400
UNIT
kHz
μs
μs
ns
ns
μs
ns
ns
ns
μs
μs
μs
μs
μs
μs
μs
pF
(1) A device internally must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH min of the SCL signal), to bridge
the undefined region of the falling edge of SCL.
(2) Cb = total bus capacitance of one bus line in pF
(3) Data taken using a 1-kΩ pull-up resistor and 50-pF load (see Figure 6)
6.7 Switching Characteristics
over recommended operating free-air temperature range, CL ≤ 100 pF (unless otherwise noted) (see Figure 5)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
MIN
MAX UNIT
tpd (1) Propagation delay time
trst (2) RESET time (SDA clear)
RON = 20 Ω, CL = 15 pF
RON = 20 Ω, CL = 50 pF
SDA or SCL
RESET
SDn or SCn
SDA
0.3
ns
1
500 ns
(1) The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load
capacitance, when driven by an ideal voltage source (zero output impedance).
(2) trst is the propagation delay measured from the time the RESET pin is first asserted low to the time the SDA pin is asserted high,
signaling a stop condition. It must be a minimum of tWL.
6
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